US2023198182A1PendingUtilityA1
MULTI-MODE AND/OR MULTI-SPEED NON-VOLATILE MEMORY (NVM) EXPRESS (NVMe) OVER FABRICS (NVMe-oF) DEVICE
Est. expiryMar 9, 2038(~11.6 yrs left)· nominal 20-yr term from priority
H01R 43/205H05K 1/181H05K 2201/10212H05K 2201/10159H01R 12/721H05K 2201/10522H01R 12/737H05K 3/303G06F 3/06H05K 2201/10545G06F 3/0634H05K 2201/10189H01R 43/26G06F 13/4068G06F 13/385G06F 3/061H04L 49/351G06F 3/0607G06F 3/0688H04L 12/02G06F 3/067G06F 3/0604G06F 9/4411G06F 3/0679G06F 3/0661G06F 3/167
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Claims
Abstract
In an example, a device includes: a printed circuit board (PCB); at least one solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) mounted on the PCB at a second side of the PCB; and at least one connector attached to the PCB at a third side of the PCB, wherein the device is configured to operate in a first speed from a plurality of operating speeds based on a first input received via the at least one connector.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A device comprising:
a processor; and a memory drive connected to the processor, wherein the device operates in a first operating mode or a second operating mode based on a first instruction, and wherein, in the second operating mode, the memory drive selects a second non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction.
2 . The device of claim 1 , further comprising a printed circuit board (PCB), wherein:
the memory drive is connected at a first side of the PCB via a connector; and the processor is mounted on the PCB at a second side of the PCB.
3 . The device of claim 2 , wherein:
the processor comprises a field programmable gate array (FPGA); the memory drive comprises a first solid state drive (SSD) and a second SSD; the connector comprises a first SSD connector and a second SSD connector; and the first SSD is connected to the PCB at the first side of the PCB via the first SSD connector and the second SSD is connected to the PCB at the first side of the PCB via the second SSD connector.
4 . The device of claim 2 , wherein:
the connector is electrically connected to the memory drive at a first side of the memory drive; and the connector is attached to the PCB at the first side of the PCB and is perpendicular to the first side of the PCB.
5 . The device of claim 2 , further comprising a structural support between the second side of the PCB and a second side of the memory drive.
6 . The device of claim 2 , wherein a length of the memory drive is about 110 mm and a length of the PCB is between 110 mm and 142 mm, and
wherein the first operating mode comprises a Non-volatile memory (NVM) express (NVMe) mode and the second operating mode comprises a NVMe over fabrics (NVMe-oF) mode.
7 . The device of claim 2 , wherein a first side of the processor is attached to the second side of the PCB, wherein the processor is electrically connected to the PCB.
8 . The device of claim 6 , further comprising a first interface layer attached at a third side of the memory drive and a second interface layer attached at a second side of the processor, wherein the first interface layer and the second interface layer are to transfer heat generated by the memory drive and the processor to outside.
9 . The device of claim 2 , wherein a length of the PCB is equal to or greater than a length of the memory drive.
10 . The device of claim 2 , wherein a length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm.
11 . The device of claim 1 , wherein the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G.
12 . The device of claim 1 , wherein the first instruction is received from a mid-plane, wherein the first instruction is controlled by two general-purpose input/output (GPIO) pins controlled by a baseboard management controller (BMC) of a switch or a local central processing unit (CPU) of a motherboard, or one or more internal registers associated with the processor.
13 . A system comprising:
a first interface layer; a memory drive attached to the first interface layer at a first side of the memory drive; a processor connected to the memory drive; and a second interface layer attached to the processor at a second side of the processor; and wherein the system operates in a first operating mode or a second operating mode based on a first instruction, wherein in the second operating mode, the system selects a first non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction, and wherein the first interface layer and the second interface layer are configured to transfer heat generated by the memory drive and the processor to outside.
14 . The system of claim 13 , further comprising a printed circuit board (PCB) connected to the memory drive at a first side of the PCB via a connector,
wherein the processor is mounted on the PCB at a second side of the PCB and a first side of the processor is attached to the PCB, wherein the connector is perpendicular to the first side of the PCB.
15 . The system of claim 14 , further comprising a structural support between the second side of the PCB and a second side of the memory drive.
16 . The system of claim 14 , wherein a length of the memory drive is about 110 mm, a length of the PCB is between 110 mm and 142 mm, and a length of the processor is about 80 mm.
17 . The system of claim 14 , wherein a length of the PCB is equal to or greater than a length of the memory drive, and wherein the length of the PCB is equal to or greater than a length of the processor.
18 . A method of operating a device comprising a processor and a memory drive connected to the processor, the method comprising:
selecting, by the device, a first operating mode or a second operating mode based on a first instruction; and in the second operating mode, selecting, by the device, a second non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction.
19 . The method of claim 18 , further comprising:
connecting the memory drive at a first side of a printed circuit board (PCB) via a connector; mounting the processor on a second side of the PCB, wherein a first side of the processor is attached to the PCB; and incorporating a structural support between the second side of the PCB and a second side of the memory drive, wherein the connector is perpendicular to the first side of the PCB.
20 . The method of claim 19 , wherein a length of the PCB is equal to or greater than a length of the memory drive, and wherein the length of the PCB is equal to or greater than a length of the processor.Join the waitlist — get patent alerts
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