Methods, devices, and systems related to forming semiconductor power devices with a handle substrate

Abstract

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

I/We claim: 
     
         1 . A semiconductor device assembly, comprising:
 a bulk substrate layer having a first length and a first width;   an intermediary material disposed over the bulk substrate layer and having a second length less than the first length and a second width less than the first width; and   a semiconductor structure coupled to the bulk substrate layer by the intermediary material and having a third length greater than the second length and a third width greater than the second width such that the semiconductor structure overhangs the intermediary material, the semiconductor structure including a transistor device having a gate region,   wherein an opening extends completely through the gate region to expose a gap between the semiconductor structure and the bulk substrate layer exclusive of the intermediary material.   
     
     
         2 . The semiconductor device assembly of  claim 1  wherein the transistor device further includes a source region and a drain region, and wherein the gate region is between the source and drain regions. 
     
     
         3 . The semiconductor device assembly of  claim 1  wherein the opening includes vertical sidewalls. 
     
     
         4 . The semiconductor device assembly of  claim 1  wherein the transistor device is a power transistor device. 
     
     
         5 . The semiconductor device assembly of  claim 1  wherein the transistor device is a high electron mobility transistor (HEMT) device. 
     
     
         6 . The semiconductor device assembly of  claim 1  wherein the bulk substrate layer comprises poly-Aluminum Nitride (p-AlN). 
     
     
         7 . The semiconductor device assembly of  claim 1 , further comprising a plurality of electrical contacts attached to the semiconductor structure and protruding away from the bulk substrate layer. 
     
     
         8 . The semiconductor device assembly of  claim 1  wherein the gap is exclusive of any solid material. 
     
     
         9 . The semiconductor device assembly of  claim 1  wherein the gap has a footprint larger than the gate region. 
     
     
         10 . The semiconductor device assembly of  claim 1  wherein the intermediary material is an oxide or a nitride. 
     
     
         11 . A semiconductor device assembly, comprising:
 a bulk substrate layer having a first footprint;   an intermediary material disposed over the bulk substrate layer and having a second footprint smaller than the first footprint; and   a semiconductor structure coupled to the bulk substrate layer by the intermediary material and having a third footprint greater than the second footprint such that the semiconductor structure overhangs the intermediary material, the semiconductor structure including a transistor device having a gate region,   wherein an opening extends completely through the gate region to expose a gap between the semiconductor structure and the bulk substrate layer exclusive of the intermediary material.   
     
     
         12 . The semiconductor device assembly of  claim 11  wherein the transistor device further includes a source region and a drain region, and wherein the gate region is between the source and drain regions. 
     
     
         13 . The semiconductor device assembly of  claim 11  wherein the opening includes vertical sidewalls. 
     
     
         14 . The semiconductor device assembly of  claim 11  wherein the transistor device is a power transistor device. 
     
     
         15 . The semiconductor device assembly of  claim 11  wherein the transistor device is a high electron mobility transistor (HEMT) device. 
     
     
         16 . The semiconductor device assembly of  claim 11  wherein the bulk substrate layer comprises poly-Aluminum Nitride (p-AlN). 
     
     
         17 . The semiconductor device assembly of  claim 11 , further comprising a plurality of electrical contacts attached to the semiconductor structure and protruding away from the bulk substrate layer. 
     
     
         18 . The semiconductor device assembly of  claim 11  wherein the gap is exclusive of any solid material. 
     
     
         19 . The semiconductor device assembly of  claim 11  wherein the gap has a footprint larger than the gate region. 
     
     
         20 . The semiconductor device assembly of  claim 11  wherein the intermediary material is an oxide or a nitride.