Stacked transistor structures with diverse gate materials

Abstract

An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.

1 . An integrated circuit comprising:
 a lower device portion including first body of semiconductor material extending horizontally between first source and drain regions;   a first gate structure around the first body, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric between the first body and the first gate electrode;   an upper device portion above the lower device portion, the upper device portion including a second body of semiconductor material spaced from the first body and extending horizontally between second source and drain regions; and   a second gate structure around the second body, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric between the second body and the second gate electrode;   wherein the first gate dielectric is compositionally distinct from the second gate dielectric.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the first gate electrode is compositionally distinct from the second gate electrode. 
     
     
         3 . The integrated circuit of  claim 2 , comprising a layer of isolation material between the first gate electrode and the second gate electrode. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the first gate dielectric includes a first native oxide on the first body and a first high-κ dielectric on the first native oxide, and wherein the second gate dielectric includes a second native oxide on the second body and a second high-κ dielectric on the second native oxide. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the first body is compositionally distinct from the second body. 
     
     
         6 . The integrated circuit of  claim 4 , comprising a dipole species in one or both of the first gate dielectric and the second gate dielectric. 
     
     
         7 . The integrated circuit of  claim 6 , wherein the dipole species comprises one or more of aluminum, barium, cerium, chromium, cobalt, dysprosium, erbium, europium, gadolinium, holmium, lanthanum, lutetium, magnesium, manganese, molybdenum, neodymium, niobium, praseodymium, samarium, scandium, strontium, terbium, thulium, titanium, ytterbium, or yttrium. 
     
     
         8 . The integrated circuit of  claim 7 , wherein the dipole species is in both the first gate dielectric and the second gate dielectric, and wherein a concentration of the dipole species in the first gate dielectric is different from a concentration of the dipole species in the second gate dielectric. 
     
     
         9 . The integrated circuit of  claim 7 , wherein the dipole species has a relatively greater concentration at an interface between the first high-κ dielectric and the first native oxide and/or at an interface between the second high-κ dielectric and the second native oxide. 
     
     
         10 . The integrated circuit of  claim 7 , wherein the dipole species is only in the first gate dielectric, the integrated circuit comprising a layer comprising titanium and nitrogen between the first gate dielectric and the first gate electrode. 
     
     
         11 . The integrated circuit of  claim 1 , wherein the first body is one of a first plurality of bodies and the second body is one of a second plurality of bodies, the first and second pluralities of bodies selected from nanowires, nanoribbons, and nanosheets. 
     
     
         12 . The integrated circuit of  claim 1 , wherein one of the lower device portion or the upper device portion is configured as an n-MOS transistor device and the other of the lower device portion and the upper device portion is configured as a p-MOS transistor device. 
     
     
         13 . An integrated circuit comprising:
 at least one first body of semiconductor material extending horizontally between and connecting a first source and a first drain;   at least one second body of semiconductor material extending horizontally between and connecting a second source and a second drain, the at least one second body arranged with the at least one first body in a spaced-apart vertical stack;   a first gate structure wrapped around the at least one first body, the first gate structure comprising a first gate electrode and a first gate dielectric wherein the first gate dielectric is between the first gate electrode and the at least one first body; and   a second gate structure wrapped around the at least one second body, the second gate structure comprising a second gate electrode and a second gate dielectric wherein the second gate dielectric is between the second gate electrode and the at least one second body;   wherein the first gate dielectric is compositionally distinct from the second gate dielectric; and   wherein the at least one first body and the at least one second body are selected from a nanowire, nanoribbon, or nanosheet.   
     
     
         14 . The integrated circuit of  claim 13 , wherein the first gate electrode is compositionally distinct from the second gate electrode. 
     
     
         15 . The integrated circuit of  claim 13 , comprising a dipole species in one or both of the first gate dielectric and the second gate dielectric, a composition of the dipole species in the first gate dielectric different from a composition of the dipole species in the second gate dielectric. 
     
     
         16 . The integrated circuit of  claim 13 , comprising a dipole species in the first gate dielectric. 
     
     
         17 . The integrated circuit of  claim 16 , wherein the dipole species is selected from aluminum, barium, cerium, chromium, cobalt, dysprosium, erbium, europium, gadolinium, holmium, lanthanum, lutetium, magnesium, manganese, molybdenum, neodymium, niobium, praseodymium, samarium, scandium, strontium, terbium, thulium, titanium, ytterbium, or yttrium. 
     
     
         18 . The integrated circuit of  claim 13 , comprising a stacked transistor structure including at least one of a n-channel transistor and at least one of a p-channel transistor. 
     
     
         19 . An integrated circuit die comprising the integrated circuit of  claim 13 . 
     
     
         20 . The integrated circuit die of  claim 19 , comprising a processor.