Chip Package Based On Through-Silicon-Via Connector And Silicon Interconnection Bridge

Abstract

A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

What is claimed is: 
     
         1 . A method for fabricating an interconnection bridge comprising:
 providing a silicon wafer with a plurality of first scribe lines extending in a first direction, a plurality of second scribe lines extending in a second direction perpendicular to the first direction and a plurality of portions each between neighboring two of the plurality of first scribe lines and between neighboring two of the plurality of second scribe lines, wherein each of the plurality of portions comprises twenty first metal bumps at a first side of a top surface of said each of the plurality of portions and twenty second metal bumps at a second side, opposite to the first side, of the top surface of said each of the plurality of portions, wherein each of the twenty first and second metal bumps comprises a first copper layer protruding from the top surface of said each of the plurality of portions, wherein the twenty first metal bumps are arranged in a first line in the first direction and the twenty second metal bumps are arranged in a second line in the first direction, wherein said each of the plurality of portions comprises twenty first metal interconnects each coupling one of the twenty first metal bumps to one of the twenty second metal bumps, wherein said one of the twenty first metal bumps and said one of the twenty second metal bumps are aligned in a third line in the second direction; and   cutting the silicon wafer along the plurality of first and second scribe lines to form one of plurality of portions as the interconnection bridge in a separated unit, wherein the interconnection bridge is configured to bond with a plurality of semiconductor integrated-circuit (IC) chips for coupling the plurality of semiconductor integrated-circuit (IC) chips.   
     
     
         2 . The method of  claim 1 , wherein said each of the plurality of portions comprises twenty third metal bumps arranged at the first side and in a fourth line in the first direction and between the first and second lines and twenty fourth metal bumps arranged at the second side and in a fifth line in the first direction and between the second and fourth lines, wherein said each of the plurality of portions further comprises twenty second metal interconnects each coupling one of the twenty third metal bumps to one of the twenty fourth metal bumps, wherein said one of the twenty third metal bumps and said one of the twenty fourth metal bumps are aligned in the third line with said one of the twenty first metal bumps and said one of the twenty second metal bumps. 
     
     
         3 . The method of  claim 2 , wherein a space between said one of the twenty third metal bumps and said one of the twenty fourth metal bumps is greater than a space between said one of the twenty first metal bumps and said one of the twenty third metal bumps and greater than a space between said one of the twenty second metal bumps and said one of the twenty fourth metal bumps. 
     
     
         4 . The method of  claim 1 , wherein the interconnection bridge has no transistor therein. 
     
     
         5 . The method of  claim 1 , wherein the interconnection bridge comprises a passive device therein. 
     
     
         6 . The method of  claim 1 , wherein said each of the twenty first and second metal bumps comprises a tin-containing solder over the first copper layer thereof. 
     
     
         7 . The method of  claim 1 , wherein the first copper layer has a thickness between 1 and 60 micrometers. 
     
     
         8 . The method of  claim 1 , wherein said each of the twenty first and second metal bumps comprises an adhesion layer at a bottom of the first copper layer thereof but not at a sidewall of the first copper layer thereof. 
     
     
         9 . The method of  claim 1 , wherein the silicon wafer comprises a silicon substrate and an interconnection scheme on the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the first interconnection metal layer, a first insulating dielectric layer between the first and second interconnection metal layers and a second insulating dielectric layer on the second interconnection metal layer, wherein the first interconnection metal layer comprises a second copper layer and a first adhesion layer at a bottom and sidewall of the second copper layer, wherein the twenty first metal interconnects are provided by the interconnection scheme. 
     
     
         10 . The method of  claim 9 , wherein the second interconnection metal layer comprises a bulk metal layer and a second adhesion layer at a bottom of the bulk metal layer thereof but not at a sidewall, over the first insulating dielectric layer, of the bulk metal layer thereof, wherein the second adhesion layer is on the first insulating dielectric layer, wherein the second insulating dielectric layer contacts the sidewall of the bulk metal layer and is over a top of the bulk metal layer, wherein the second interconnection metal layer comprises a plurality of metal pads each at a bottom of one of a plurality of openings in the second insulating dielectric layer, wherein each of the twenty first and second metal bumps is on a metal pad of the plurality of metal pads and over an opening of the plurality of openings and couples to the metal pad through the opening. 
     
     
         11 . The method of  claim 1 , wherein the silicon wafer comprises a third scribe line extending in the second direction and between neighboring two of the plurality of second scribe lines, wherein while said cutting the silicon wafer along the plurality of first and second scribe lines, the silicon wafer is not cut along the third scribe line, wherein the third scribe line is reserved in the interconnection bridge. 
     
     
         12 . A method for fabricating an interconnection bridge comprising:
 providing a silicon wafer with a plurality of first scribe lines extending in a first direction, a plurality of second scribe lines extending in a second direction perpendicular to the first direction and a plurality of portions each between neighboring two of the plurality of first scribe lines and between neighboring two of the plurality of second scribe lines, wherein the silicon wafer comprises a silicon substrate and an interconnection scheme on the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the first interconnection metal layer, a first insulating dielectric layer between the first and second interconnection metal layers and a second insulating dielectric layer on the second interconnection metal layer, wherein the first interconnection metal layer comprises a first copper layer and a first adhesion layer at a bottom and sidewall of the first copper layer, wherein the second interconnection metal layer comprises a bulk metal layer and a second adhesion layer at a bottom of the bulk metal layer thereof but not at a sidewall, over the first insulating dielectric layer, of the bulk metal layer thereof, wherein the second adhesion layer is on the first insulating dielectric layer and the second insulating dielectric layer contacts the sidewall of the bulk metal layer and is over a top of the bulk metal layer, wherein the second interconnection metal layer comprises a plurality of metal pads each at a bottom of one of a plurality of openings in the second insulating dielectric layer, wherein each of the plurality of portions comprises twenty first metal bumps at a first side of a top surface of said each of the plurality of portions and twenty second metal bumps at a second side, opposite to the first side, of the top surface of said each of the plurality of portions, wherein each of the twenty first and second metal bumps is on a metal pad of the plurality of metal pads and over an opening of the plurality of openings and couples to the metal pad through the opening, wherein said each of the twenty first and second metal bumps comprises a second copper layer over the second insulating layer and in the opening and a third adhesion layer between the second copper layer thereof and the metal pad and between the second copper layer thereof and the second insulating dielectric layer, wherein the third adhesion layer is at a bottom of the second copper layer but not at a sidewall, over the second insulating dielectric layer, of the second copper layer, wherein said each of the plurality of portions comprises twenty first metal interconnects each coupling one of the twenty first metal bumps to one of the twenty second metal bumps, wherein the twenty first metal interconnects are provided by the interconnection scheme; and   cutting the silicon wafer along the plurality of first and second scribe lines to form one of the plurality of portions as the interconnection bridge in a separated unit, wherein the interconnection bridge is configured to bond with a plurality of semiconductor integrated-circuit (IC) chips for coupling the plurality of semiconductor integrated-circuit (IC) chips.   
     
     
         13 . The method of  claim 12 , wherein the twenty first metal bumps are arranged in a first line in the first direction, the twenty second metal bumps are arranged in a second line in the first direction and said one of the twenty first metal bumps and said one of the twenty second metal bumps are aligned in a third line in the second direction. 
     
     
         14 . The method of  claim 13 , wherein said each of the plurality of portions comprises twenty third metal bumps arranged at the first side and in a fourth line in the first direction and between the first and second lines and twenty fourth metal bumps arranged at the second side and in a fifth line in the first direction and between the second and fourth lines, wherein said each of the plurality of portions further comprises twenty second metal interconnects each coupling one of the twenty third metal bumps to one of the twenty fourth metal bumps, wherein said one of the twenty third metal bumps and said one of the twenty fourth metal bumps are aligned in the third line with said one of the twenty first metal bumps and said one of the twenty second metal bumps. 
     
     
         15 . The method of  claim 14 , wherein a space between said one of the twenty third metal bumps and said one of the twenty fourth metal bumps is greater than a space between said one of the twenty first metal bumps and said one of the twenty third metal bumps and greater than a space between said one of the twenty second metal bumps and said one of the twenty fourth metal bumps. 
     
     
         16 . The method of  claim 12 , wherein the interconnection bridge has no transistor therein. 
     
     
         17 . The method of  claim 12 , wherein the interconnection bridge comprises a passive device therein. 
     
     
         18 . The method of  claim 12 , wherein said each of the twenty first and second metal bumps comprises a tin-containing solder over the second copper layer thereof. 
     
     
         19 . The method of  claim 12 , wherein the second copper layer has a thickness between 1 and 60 micrometers. 
     
     
         20 . The method of  claim 12 , wherein the second adhesion layer comprises titanium. 
     
     
         21 . The method of  claim 12 , wherein the silicon wafer comprises a third scribe line extending in the second direction and between neighboring two of the plurality of second scribe lines, wherein while said cutting the silicon wafer along the plurality of first and second scribe lines, the silicon wafer is not cut along the third scribe line, wherein the third scribe line is reserved in the interconnection bridge.