Via in semiconductor device structure

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer. The semiconductor device structure includes an insulating capping layer formed over the gate electrode layer, and the insulating capping layer covers a top surface of the gate dielectric layer. The semiconductor device structure also includes a conductive via structure formed through the insulating capping layer, and a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.

What is claimed is: 
     
         1 . A semiconductor device structure, comprising:
 a gate structure formed over a substrate, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer;   an insulating capping layer formed over the gate electrode layer, wherein the insulating capping layer covers a top surface of the gate dielectric layer; and   a conductive via structure formed through the insulating capping layer, wherein a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.   
     
     
         2 . The semiconductor device structure as claimed in  claim 1 , wherein the gate structure further comprises a gate spacer, and the portion of the conductive via structure is lower than a top surface of the gate spacer. 
     
     
         3 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 a source/drain (S/D) contact structure formed adjacent to the gate structure, wherein a top surface of the S/D contact structure is lower than the top surface of the gate dielectric layer.   
     
     
         4 . The semiconductor device structure as claimed in  claim 3 , further comprising:
 a second conductive via structure formed on the S/D contact structure, wherein the second conductive via structure has a step-shaped structure.   
     
     
         5 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 a conductive layer formed over the gate electrode layer, wherein the conductive layer is in direct contact with the conductive via structure.   
     
     
         6 . The semiconductor device structure as claimed in  claim 5 , wherein a top surface of the conductive layer is lower than the top surface of the gate dielectric layer. 
     
     
         7 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 a first insulating layer formed over the insulating capping layer, wherein a portion of the first insulating layer is lower than top surface of the gate dielectric layer.   
     
     
         8 . The semiconductor device structure as claimed in  claim 7 , further comprising:
 a second insulating layer formed over the first insulating layer, wherein the conductive via structure penetrates through the first insulating layer and the second insulating layer.   
     
     
         9 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 a gate cut structure formed adjacent to the gate structure, wherein a top surface of the gate cut structure is higher than a top surface of the gate electrode layer.   
     
     
         10 . A semiconductor device structure, comprising:
 a gate structure formed over a substrate,   a gate spacer formed adjacent to the gate structure;   a source/drain (S/D) contact structure formed adjacent to the gate spacer; and   a conductive via structure formed over the S/D contact structure, wherein the conducive via structure is in direct contact with the gate spacer.   
     
     
         11 . The semiconductor device structure as claimed in  claim 10 , further comprising:
 an insulating capping layer formed over the gate structure, wherein the conductive via structure is in direct contact with a top surface and a sidewall surface of the insulating capping layer.   
     
     
         12 . The semiconductor device structure as claimed in  claim 11 , wherein the insulating capping layer has a T-shaped structure. 
     
     
         13 . The semiconductor device structure as claimed in  claim 11 , wherein a sidewall of the gate spacer is substantially aligned to a sidewall of the insulating capping layer. 
     
     
         14 . The semiconductor device structure as claimed in  claim 10 , further comprising:
 a gate cut structure formed adjacent to the gate structure, wherein a top surface of the gate cut structure is higher than a top surface of a gate electrode layer of the gate structure.   
     
     
         15 . The semiconductor device structure as claimed in  claim 10 , wherein the conductive via structure has a step-shaped structure. 
     
     
         16 . The semiconductor device structure as claimed in  claim 10 , wherein a top surface of the gate spacer is higher than a top surface of the S/D contact structure. 
     
     
         17 . A semiconductor device structure, comprising
 a gate structure formed over a substrate;   a conductive layer formed on the gate structure;   a gate spacer formed adjacent to the gate structure;   a source/drain (S/D) contact structure formed adjacent to the gate spacer; and   an insulating capping layer formed on the gate spacer and the gate structure, wherein the insulating capping layer is in direct contact with a top surface of the gate spacer and the conductive layer.   
     
     
         18 . The semiconductor device structure as claimed in  claim 17 , wherein an interface between the conducive layer and the insulating capping layer is lower than the top surface of the gate spacer. 
     
     
         19 . The semiconductor device structure as claimed in  claim 17 , further comprising:
 an S/D contact structure formed adjacent to the gate structure; and   a conductive via structure formed on the S/D contact structure, wherein a portion of the conductive via structure is in direct contact with the insulating capping layer.   
     
     
         20 . The semiconductor device structure as claimed in  claim 17 , further comprising:
 a first insulating layer formed over the S/D contact structure and the insulating capping layer, wherein a portion of the first insulating layer is lower than top surface of the gate spacer.