US2023197504A1PendingUtilityA1

Method for forming a shallow trench isolation structure with reduced encroachment of active regions and a semiconductor structure therefrom

Assignee: NANYA TECHNOLOGY CORPPriority: Aug 25, 2021Filed: Feb 22, 2023Published: Jun 22, 2023
Est. expiryAug 25, 2041(~15.1 yrs left)· nominal 20-yr term from priority
H10P 95/062H10W 10/17H10W 10/014H01L 21/31053H01L 21/76224H01L 27/10H10D 84/00
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Claims

Abstract

A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a silicon substrate;   a plurality of first trenches with one or more sizes filled with a first dielectric material formed in the silicon substrate along a first dimension;   a plurality of second trenches with one or more sizes filled with a second dielectric material formed in the silicon substrate along a second dimension; and   a plurality of active regions with one or more sizes formed in the silicon substrate, wherein each of the active regions is rectangular-shaped with round corners and separated from each other by the first trenches filled with the first dielectric material and the second trenches filled with the second dielectric material.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first trench has a different size from that of the second trench. 
     
     
         3 . The semiconductor structure of  claim 1 , where the first trenches are interdigitated with the second trenches.

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