Systems and methods of eliminating connectivity mismatches in a mask layout block

Abstract

Computer-implemented systems and methods for automatically eliminating connectivity mismatches in a mask layout block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints. Disclosed systems and methods analyze a physical connection of a selected polygon or net in a mask layout block and obtain connectivity information associated with the selected polygon or net from a netlist or external constraints file. The physical connection of the selected polygon or net is compared with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net. If there is a determined connectivity mismatch, a violation marker representing the connectivity mismatch is generated and the connectivity mismatch is corrected by placing, moving, or editing the selected polygon or net to modify the physical connection.

What is claimed is: 
     
         1 . A computer-implemented method of automatically eliminating connectivity mismatches in a mask layout block, comprising:
 analyzing a physical connection of a selected polygon or net in a mask layout block;   obtaining connectivity information associated with the selected polygon or net from an external source;   comparing the physical connection of the selected polygon or net with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net;   if there is a determined connectivity mismatch, generating a violation marker representing the connectivity mismatch; and   correcting the connectivity mismatch by placing, moving, or editing the selected polygon or net to modify the physical connection;   wherein the step of correcting the connectivity mismatch further comprises one or more of:
 disconnecting the physical connection, erasing all net connections, locating correct layout nodes in the mask layout block, or creating a new physical connection between matched layout nodes. 
   
     
     
         2 . The computer-implemented method of  claim 1  wherein the external source is a netlist or external constraints file. 
     
     
         3 . The computer-implemented method of  claim 1  wherein the analyzing step is performed during construction of the mask layout block. 
     
     
         4 . The computer-implemented method of  claim 1  further comprising generating an LVS clean mask layout database during construction of the mask layout block. 
     
     
         5 . The computer-implemented method of  claim 1  further comprising determining if the modified physical connection creates a process design rule violation; and
 if a process design rule violation is created, eliminating the process design rule violation by further modifying the modified physical connection. 
 
     
     
         6 . The computer-implemented method of  claim 1  further comprising providing an information window showing the connectivity information. 
     
     
         7 . The computer-implemented method of  claim 1  further comprising generating a fly-line marker representing a corrected position for the selected polygon or net. 
     
     
         8 . A computer-implemented system for automatic elimination of connectivity mismatches in a mask layout block, comprising:
 a processor; and   a computer readable memory in communication with the processor, the computer readable memory containing processing instructions;   the processing instructions providing for analysis of a physical connection of a selected polygon or net in a mask layout block and for retrieval of connectivity information associated with the selected polygon or net from a netlist or external constraints file;   the mask layout block and the netlist or external constraints file being hierarchical, and the mask layout block including at least one top-level cell and at least one sub-cell located in the top-level cell;   the processing instructions providing for comparison of the physical connection of the selected polygon or net in one or more instances of the at least one sub-cell with the retrieved connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net in one or more instances of the at least one sub-cell;   if there is a determined connectivity mismatch in one or more instances of the at least one sub-cell, the processing instructions providing for generation of a violation marker representing the connectivity mismatch and for correction of the connectivity mismatch by placing, moving, or editing the selected polygon or net to modify the physical connection.   
     
     
         9 . The computer-implemented system of  claim 8  wherein if there is a determined connectivity mismatch, the processing instructions prevent placement of the selected polygon or net in the mask layout block at a position that would create the connectivity mismatch. 
     
     
         10 . The computer-implemented system of  claim 8  further comprising an information window in communication with the computer readable memory and the processor;
 wherein the connectivity information and the violation marker are visible in the information window; and 
 wherein a fly-line marker representing a corrected position for the selected polygon or net is visible in the information window. 
 
     
     
         11 . A layout editor interfaced tool for automatic elimination of connectivity mismatches in a mask layout block, comprising:
 a processor; and   a computer readable memory in communication with the processor, the computer readable memory containing processing instructions;   the layout editor interfaced tool analyzing the mask layout block for electrical connectivity and determining if a connectivity mismatch has been made;   the layout editor interfaced tool providing operation in Advice mode, Correct mode, and Auto-Fix mode;   wherein when operating in Advice mode, the layout editor interfaced tool displays an Advice marker showing connectivity information;   wherein when operating in Correct mode, the layout editor interfaced tool enforces connectivity mismatch elimination by automatically making all polygons or nets connectivity correct; and   wherein when operating in Auto-Fix mode, the layout editor interfaced tool analyzes the mask layout block for connectivity mismatches and provides an Auto-Correction feature.   
     
     
         12 . The layout editor interfaced tool of  claim 11  further comprising a convolutional neural network performing deep learning of the mask layout block, analysis, and automatic correction.