Memory cell, memory device, and methods thereof

Abstract

Various aspects relate to a memory cell, the memory cell including: a field-effect transistor structure; and a capacitive memory structure; wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider; wherein the capacitive memory structure includes: a first electrode layer, a second electrode layer, and a memory element structured to have at least a first region extending from the first electrode layer to the second electrode layer and a second region extending from the first electrode layer to the second electrode layer, wherein the first region consists of a first material, wherein the second region consists of a second material, and wherein the first material is different from the second material.

What is claimed is: 
     
         1 . A memory cell comprising:
 a field-effect transistor structure; and   a capacitive memory structure;   wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider;   wherein the capacitive memory structure comprises:   a first electrode layer, a second electrode layer, and a memory element structured to have at least a first region extending from the first electrode layer to the second electrode layer and a second region extending from the first electrode layer to the second electrode layer,   wherein the first region consists of a first material,   wherein the second region consists of a second material, and   wherein the first material is different from the second material.   
     
     
         2 . The memory cell according to  claim 1 ,
 wherein the first material differs from the second material in at least one of a chemical composition, a porosity, and/or a crystal structure.   
     
     
         3 . The memory cell according to  claim 1 ,
 wherein the first material comprises a spontaneously-polarizable material, and   wherein the second region is substantially free of a spontaneously-polarizable material.   
     
     
         4 . The memory cell according to  claim 1 ,
 wherein the first material comprises a base material having a first concentration of dopant elements,   wherein the second material comprises the base material having a second concentration of dopant elements different from the first concentration of dopant elements or wherein the second material comprises the base material having substantially no dopant elements.   
     
     
         5 . The memory cell according to  claim 1 ,
 wherein the first region comprises at least a single grain of a spontaneously-polarizable material that is in contact with both the first electrode layer and the second electrode layer, and   wherein the second region is free of a single grain of a spontaneously-polarizable material that is in contact with both the first electrode layer and the second electrode layer.   
     
     
         6 . The memory cell according to  claim 1 ,
 wherein the first region comprises a first metal oxide,   wherein the second region comprises a second metal oxide, and   wherein the first metal oxide differs from the second metal oxide in at least one of chemical composition and/or crystal structure.   
     
     
         7 . The memory cell according to  claim 1 ,
 wherein the first region has a first remanent polarization associated therewith, and   wherein the second region has a second remanent polarization associated therewith less than the first remanent polarization or wherein the second region is non-remanently polarizable.   
     
     
         8 . The memory cell according to  claim 1 ,
 wherein an actual depolarization field value associated with the capacitive memory structure is defined by polarization characteristics of the first region and the second region, and   wherein the actual depolarization field value is less than a depolarization field value associated with the first region defined by a material-specific polarization characteristic of the first material.   
     
     
         9 . The memory cell according to  claim 1 ,
 wherein the first region has a width less than a width of the first electrode layer and less than a width of the second electrode layer.   
     
     
         10 . The memory cell according to  claim 1 ,
 wherein the memory element further comprises a separation structure disposed between the first region and the second region.   
     
     
         11 . A memory cell comprising:
 a field-effect transistor structure; and   a capacitive memory structure;   wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider;   wherein the capacitive memory structure is configured as a parallel connection of one or more spontaneously-polarizable capacitors and one or more dielectric capacitors.   
     
     
         12 . The memory cell according to  claim 11 ,
 wherein the capacitive memory structure comprises:   a first continuous electrode layer, and   a second continuous electrode layer, and   wherein the one or more spontaneously-polarizable capacitors and the one or more dielectric capacitors share as common nodes the first continuous electrode layer and the second continuous electrode layer.   
     
     
         13 . A method of forming a memory cell, the method comprising:
 forming a field-effect transistor structure and a capacitive memory structure in a capacitive voltage divider configuration;   wherein forming the capacitive memory structure comprises:   forming a first electrode layer;   forming a first region of a memory element and, subsequently, forming a second region of the memory element; and   forming a second electrode layer,   wherein the first region of the memory element is in direct physical contact with the first electrode layer and the second electrode layer and wherein the second region of the memory element is in direct physical contact with the first electrode layer and the second electrode layer.   
     
     
         14 . The method according to  claim 13 ,
 wherein forming the first region of the memory element comprises depositing a first material by a first deposition process, and   wherein forming the second region of the memory element comprises depositing a second material by a second deposition process different from the first deposition process.   
     
     
         15 . The method according to  claim 13 ,
 wherein forming the first region of the memory element and, subsequently, forming the second region of the memory element comprises depositing a base material by a deposition process and partially modifying the base material to thereby form the first region and, subsequently, the second region of the memory element.   
     
     
         16 . The method according to  claim 13 ,
 wherein the first region consists of a first material,   wherein the second region consists of a second material, and   wherein the first material differs from the second material in at least one of a chemical composition, a porosity, and/or a crystal structure.   
     
     
         17 . The method according to  claim 13 ,
 wherein forming the first region and, subsequently, the second region of the memory element comprises:   forming a layer of dielectric material on the first electrode layer;   removing at least part of the layer of dielectric material to provide a cavity in the layer of dielectric material exposing the first electrode layer; and   forming a layer of spontaneously-polarizable material in the cavity.   
     
     
         18 . The method according to  claim 13 ,
 wherein forming the first region and, subsequently, the second region of the memory element comprises:   forming a layer of a base material on the first electrode layer in such a way that the layer has at least a first portion having a first height and a second portion having a second height different from the first height.   
     
     
         19 . The method according to  claim 13 ,
 wherein forming the first region and, subsequently, the second region of the memory element comprises:   forming a layer of a base material on the first electrode layer, and   introducing one or more dopant elements in at least a portion of the layer to modify a crystal structure of the portion.   
     
     
         20 . The method according to  claim 18 ,
 wherein forming the first region and, subsequently, the second region of the memory element further comprises:   inducing a crystallization of the layer of the base material to obtain or maintain spontaneously-polarizable properties in the base material of the first portion and to obtain or maintain non-spontaneously-polarizable properties in the base material of the second portion.