Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternatively, the stacked body including a staircase portion obtained by processing the plurality of first conductive layers in a staircase pattern; a pillar extending in a stacking direction of the stacked body in the stacked body away from the staircase portion in a first direction intersecting the stacking direction; and a contact disposed in the staircase portion and connected to one first conductive layer out of the plurality of first conductive layers, in which the contact includes a second conductive layer extending from above the staircase portion to the one first conductive layer and integrated with the one first conductive layer.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternatively, the stacked body including a staircase portion obtained by processing the plurality of first conductive layers in a staircase pattern;   a pillar extending in a stacking direction of the stacked body in the stacked body away from the staircase portion in a first direction intersecting the stacking direction, the pillar forming a memory cell at an intersection with at least a part of each of the plurality of first conductive layers; and   a contact disposed in the staircase portion and connected to one first conductive layer out of the plurality of first conductive layers, wherein   the contact includes a second conductive layer extending from above the staircase portion to the one first conductive layer, the second conductive layer being integrated with the one first conductive layer.   
     
     
         2 . The semiconductor memory device according to  claim 1 , further comprising:
 a second insulating layer covering the staircase portion at least up to a height of an uppermost layer of the stacked body; and   a first layer disposed in the second insulating layer along a shape of the staircase portion, the first layer being of a type different from a type of at least the second insulating layer, wherein   the contact includes a liner layer covering a side wall of the second conductive layer and extending to at least a position below the first layer.   
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein the liner layer is a layer having selectivity in dry etching against the first layer. 
     
     
         4 . The semiconductor memory device according to  claim 3 ,
 wherein the liner layer is a fourth insulating layer of the same type as the second insulating layer.   
     
     
         5 . The semiconductor memory device according to  claim 2 ,
 wherein the liner layer is a layer having selectivity in wet etching against the second insulating layer.   
     
     
         6 . The semiconductor memory device according to  claim 5 ,
 wherein the liner layer is a third conductive layer containing metal.   
     
     
         7 . The semiconductor memory device according to  claim 2 , wherein 
 the contact includes a metal-containing insulating layer interposed between the second conductive layer and the liner layer, the metal-containing insulating layer extending inner side of the second insulating layer in the stacking direction, and   the metal-containing insulating layer penetrates the second insulating layer below the first layer.   
     
     
         8 . The semiconductor memory device according to  claim 7 , wherein
 the metal-containing insulating layer continuously extends from a side wall of the second conductive layer to an upper surface of the one first conductive layer excluding a connection surface with the contact.   
     
     
         9 . The semiconductor memory device according to  claim 8 , wherein
 the contact includes a fourth conductive layer interposed between the second conductive layer and the metal-containing insulating layer and extending inner side of the second insulating layer in the stacking direction, and   the fourth conductive layer penetrates the second insulating layer below the first layer.   
     
     
         10 . The semiconductor memory device according to  claim 9 , wherein
 the fourth conductive layer continuously extends inner side of the metal-containing insulating layer from a side wall of the second conductive layer to the upper surface of the one first conductive layer excluding the connection surface with the contact.   
     
     
         11 . A method of manufacturing a semiconductor memory device, the method comprising:
 forming a first stacked body in which a plurality of sacrificial layers and a plurality of first insulating layers are stacked alternatively, the first stacked body including a staircase portion obtained by processing the plurality of sacrificial layers in a staircase pattern;   forming a pillar including a semiconductor layer and a memory layer, the semiconductor layer extending in a stacking direction of the first stacked body in the first stacked body away from the staircase portion in a first direction intersecting the stacking direction, the memory layer covering a side wall of the semiconductor layer;   forming a plurality of contact holes being arranged in the staircase portion and reaching the plurality of sacrificial layers respectively;   removing the plurality of sacrificial layers via the plurality of contact holes to form a second stacked body having a plurality of gap layers each being disposed between the plurality of first insulating layers, and   filling the plurality of gap layers and the plurality of contact holes with a conductive material via the plurality of contact holes to form a third stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternatively as well as forming a plurality of contacts connected to each of the plurality of first conductive layers.   
     
     
         12 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising:
 forming a slit extending in the stacking direction and the first direction in the first stacked body, wherein
 removing, when forming the second stacked body, the plurality of sacrificial layers through the slit together with the plurality of contact holes; and 
 filling, when forming the third stacked body and the plurality of contacts, the plurality of gap layers with the conductive material through the slit together with the plurality of contact holes. 
   
     
     
         13 . The method of manufacturing a semiconductor memory device according to  claim 11 , wherein
 forming, when forming the third stacked body and the plurality of contacts, a second conductive layer to be filled in each of the plurality of contact holes and integrated with each of the plurality of first conductive layers.   
     
     
         14 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising:
 forming a second insulating layer covering the staircase portion at least up to a height of an uppermost layer of the first stacked body while interposing, in the second insulating layer, a first layer different in type from at least the second insulating layer along a shape of the staircase portion, wherein
 performing, when forming the plurality of contact holes, dry etching using the first layer as an etch stopper layer to cause the plurality of contact holes to penetrate through the second insulating layer above the first layer to reach the first layer having different depth positions in the second insulating layer; and 
 performing after causing the plurality of contact holes to reach the first layer, dry etching on the first layer to cause the contact holes to reach at least different depth positions below the first layer, individually. 
   
     
     
         15 . The method of manufacturing a semiconductor memory device according to  claim 14 , wherein
 forming, when forming the plurality of contact holes, a liner layer covering side walls of each of the plurality of contact holes and bottom surfaces of each of the plurality of contact holes located at different depths below the first layer; and   performing dry etching using the plurality of sacrificial layers as etch stopper layers to cause the plurality of contact holes to penetrate through the liner layer on the bottom surfaces of the plurality of contact holes and the second insulating layer below the first layer to individually reach the plurality of sacrificial layers.   
     
     
         16 . The method of manufacturing a semiconductor memory device according to  claim 15 ,
 wherein the liner layer is a fourth insulating layer of the same type as the second insulating layer.   
     
     
         17 . The method of manufacturing a semiconductor memory device according to  claim 14 , wherein
 forming, when forming the plurality of contact holes, a liner layer covering side walls of each of the plurality of contact holes and bottom surfaces of each of the plurality of contact holes located at different depths below the first layer;   performing dry etching using the second insulating layer below the first layer as an etch stopper layer to cause the plurality of contact holes to penetrate the liner layer on the bottom surfaces of the plurality of contact holes to reach the second insulating layer below the first layer; and   performing wet etching using the plurality of sacrificial layers as an etch stopper layer to penetrate through the second insulating layer below the first layer on the bottom surfaces of the plurality of contact holes to cause the plurality of contact holes to individually reach the plurality of sacrificial layers.   
     
     
         18 . The method of manufacturing a semiconductor memory device according to  claim 17 ,
 wherein the liner layer is a third conductive layer containing metal.   
     
     
         19 . The method of manufacturing a semiconductor memory device according to  claim 11 , wherein
 forming, when forming the third stacked body and the plurality of contacts, a metal-containing insulating layer that covers a side wall at least at a lower end of each of the plurality of contact holes and continuously extends from a side wall of each of the plurality of contact holes to a surface of each of the plurality of first insulating layers facing each other on both sides in the stacking direction across the plurality of gap layers.   
     
     
         20 . The method of manufacturing a semiconductor memory device according to  claim 19 , wherein
 forming, when forming the third stacked body and the plurality of contacts, a fourth conductive layer that covers a side wall of each of the plurality of contact holes via the metal-containing insulating layer and continuously extends inside the metal-containing insulating layer from a side wall of each of the plurality of contact holes to a surface of each of the plurality of first insulating layers facing each other on both sides in the stacking direction across the plurality of gap layers.