In-situ feedback for localized compensation

Abstract

Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.

What is claimed is: 
     
         1 . A method of using a processor to control an in-situ feedback tool to perform process-based compensation, the method comprising:
 directing one or more sensors of the in-situ feedback tool to measure a property of each of a plurality of test structures on a surface of a semiconductor wafer;   determining, by the processor, a local condition of the semiconductor wafer for each measured property of the plurality of test structures;   determining, by the processor, a localized process-based compensation for each local condition; and   directing a lithography module to provide, for each local condition, the respective localized process-based compensation on the surface of the semiconductor wafer.   
     
     
         2 . The method of  claim 1 , wherein the property of each respective test structure comprises a height, a size, a shape, or a reflectivity of the test structure. 
     
     
         3 . The method of  claim 2 , wherein the local condition comprises a topography variation or a degree of wafer bow of the semiconductor wafer. 
     
     
         4 . The method of  claim 3 , wherein the localized process-based compensation comprises one or more of a focus adjustment of the lithography module, a resist volume adjustment of the lithography module, and an exposure setting adjustment of the lithography module. 
     
     
         5 . The method of  claim 1  further comprising building, by the processor, a compensation mapping based on the measured properties of each of the plurality of test structures. 
     
     
         6 . The method of  claim 1 , wherein the test structures are uniformly spaced across the surface of the semiconductor wafer. 
     
     
         7 . The method of  claim 1 , wherein a density of test structures is greater in a first region of the semiconductor wafer than in a second region of the semiconductor wafer. 
     
     
         8 . The method of  claim 7 , wherein the density of test structures is greater along a perimeter of the semiconductor wafer than in a center region of the semiconductor wafer. 
     
     
         9 . The method of  claim 7 , wherein the density of test structures is lower along a perimeter of the semiconductor wafer than in a center region of the semiconductor wafer. 
     
     
         10 . The method of  claim 1 , wherein a size of the test structures varies across the surface of the semiconductor wafer. 
     
     
         11 . The method of  claim 1 , wherein an edge-to-edge pitch between test structures varies across the surface of the semiconductor wafer. 
     
     
         12 . A method for forming a semiconductor device, the method comprising:
 forming a first test structure and a second test structure on a surface of a semiconductor wafer;   measuring, by an in-situ feedback tool, a first height of the first test structure and a second height of the second test structure;   comparing a difference between the first height and the second height to a predetermined threshold; and   in response to the difference in heights satisfying the predetermined threshold, providing a localized process-based compensation on the surface of the semiconductor wafer.   
     
     
         13 . The method of  claim 12  further comprising determining a change in topography of the semiconductor wafer based on the measured first height and the measured second height. 
     
     
         14 . The method of  claim 12  further comprising determining a degree of wafer bow of the semiconductor wafer based on the measured first height and the measured second height. 
     
     
         15 . The method of  claim 12 , wherein the predetermined threshold comprises a difference in height of at least 5 microns. 
     
     
         16 . The method of  claim 12 , wherein the localized process-based compensation comprises one or more of a lithography focus adjustment, a resist volume adjustment, and an exposure setting adjustment. 
     
     
         17 . A semiconductor fabrication system for in-situ process-based compensation, the system comprising:
 an in-situ feedback tool comprising one or more sensors;   a lithography module; and   a processor, the processor configured to:
 direct the one or more sensors of the in-situ feedback tool to measure a property of each of a plurality of test structures on a surface of a semiconductor wafer; 
 determine a local condition of the semiconductor wafer for each measured property of the plurality of test structures; 
 determine a localized process-based compensation for each local condition; and 
 direct the lithography module to provide, for each local condition, the respective localized process-based compensation on the surface of the semiconductor wafer. 
   
     
     
         18 . The system of  claim 17 , wherein the property of each respective test structure comprises a height, a size, a shape, or a reflectivity of the test structure. 
     
     
         19 . The system of  claim 17 , wherein the local condition comprises a topography variation or a degree of wafer bow of the semiconductor wafer. 
     
     
         20 . The system of  claim 17 , wherein the localized process-based compensation comprises one or more of a focus adjustment of the lithography module, a resist volume adjustment of the lithography module, and an exposure setting adjustment of the lithography module.