Recessed inner gate spacers and partial replacement channel in non-planar transistors

Abstract

A semiconductor structure includes a body including semiconductor material, and a gate structure at least in part wrapped around the body. The semiconductor structure further includes a source region and a drain region, the body laterally extending between the source and drain regions. The body has a middle region between first and second tip regions. In an example, the source region at least in part wraps around the first tip region of the body, and/or the drain region at least in part wraps around the second tip region of the body. In another example, the body includes a core structure and a peripheral structure (e.g., cladding or layer that wraps around the core structure in the middle region of the body) that is compositionally different from the core structure. The body can be, for instance, a nanoribbon, nanosheet, or nanowire or a gate-all-around device or a forksheet device.

1 . A semiconductor structure comprising:
 a body comprising a semiconductor material;   a gate structure at least in part wrapped around the body, the gate structure including (i) a gate electrode and (ii) a gate dielectric between the body and the gate electrode; and   a source region and a drain region, the body laterally extending between the source and drain regions,   wherein the body has a first tip region, a second tip region, and a middle region between the first and second tip regions, and   wherein the source region at least in part wraps around the first tip region of the body, and/or the drain region at least in part wraps around the second tip region of the body.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the source region at least in part wraps around the first tip region of the body and the drain region at least in part wraps around the second tip region of the body. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the body is a first body, the middle region is a first middle region, and wherein the semiconductor structure further comprises:
 a second body comprising a semiconductor material and laterally extending between the source and drain regions, wherein the second body has a third tip region, a fourth tip region, and a second middle region between the third and fourth tip regions,   wherein at least a section of the source region is vertically between the first tip region of the first body and the third tip region of the second body.   
     
     
         4 . The semiconductor structure of  claim 3 , wherein at least a section of the drain region is vertically between the second tip region of the first body and the fourth tip region of the second body. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein:
 the body has a first near-tip region laterally between the first tip region and the middle region, and a second near-tip region laterally between the second tip region and the middle region;   the semiconductor structure further comprises a first inner gate spacer between the gate electrode and the source region, and a second inner gate spacer between the gate electrode and the drain region; and   the first inner gate spacer above and below the first near-tip region.   
     
     
         6 . The semiconductor structure of  claim 5 , further comprising:
 a first gate spacer and a second gate spacer, an upper section of the gate electrode between the first and second gate spacers,   wherein a width of the first gate spacer is at least 5% more than a width of the first inner gate spacer, the width measured in a direction that is parallel to a length of the body.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein:
 the body comprises (i) a core structure that includes the first tip region, the second tip region, and a section of the middle region, and (ii) a peripheral structure that includes another section of the middle region, the peripheral structure compositionally different from the core structure.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the peripheral structure wraps around the core structure in the middle region of the body. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein:
 the core structure comprises group IV semiconductor material; and   the peripheral structure comprises group III-V semiconductor material.   
     
     
         10 . The semiconductor structure of  claim 7 , wherein:
 the core structure comprises group IV semiconductor material; and   the peripheral structure comprises group IV semiconductor material.   
     
     
         11 . The semiconductor structure of  claim 1 , wherein the body is part of a vertical stack including two or more nanosheets or nanoribbons. 
     
     
         12 . A semiconductor structure comprising:
 a body comprising a semiconductor material;   a gate structure at least in part wrapped around the body, the gate structure including (i) a gate electrode and (ii) a gate dielectric between the body and the gate electrode; and   a source region and a drain region, the body laterally extending between the source and drain regions,   wherein the body has a first tip region, a second tip region, and a middle region laterally between the first and second tip regions,   wherein the body comprises (i) a core structure that includes the first tip region, the second tip region, and a section of the middle region, and (ii) a peripheral structure that includes another section of the middle region, the peripheral structure compositionally different from the core structure, and   wherein the peripheral structure wraps around the core structure in the middle region of the body.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein:
 the core structure comprises a continuous section having one end abutting the source region and another end abutting the drain region;   the peripheral structure is confined within the middle region of the body and is absent from the first and second tip regions of the body; and   the peripheral structure is in between and separates the gate dielectric and the core structure.   
     
     
         14 . The semiconductor structure of  claim 12 , wherein:
 the core structure has a first vertical height in the first tip region and a second vertical height in the middle region, wherein the first and second vertical heights are measured in a direction that is perpendicular to a length of the body; and   the first vertical height is at least 5% more than the second vertical height.   
     
     
         15 . The semiconductor structure of  claim 12 , wherein:
 a first vertical height of the middle region of the body is within 5% of a second vertical height of the first tip region of the body, wherein the first and second vertical heights are measured in a direction that is perpendicular to a length of the body.   
     
     
         16 . The semiconductor structure of  claim 12 , wherein:
 wherein the source region at least in part wraps around the first tip region of the body, and the drain region at least in part wraps around the second tip region of the body.   
     
     
         17 . The semiconductor structure of  claim 12 , wherein the body is a first body, the middle region is a first middle region, and wherein the semiconductor structure further comprises:
 a second body comprising a semiconductor material and laterally extending between the source and drain regions, wherein the second body has a third tip region, a fourth tip region, and a second middle region laterally between the first and second tip regions,   wherein at least a section of the source region is vertically between the first tip region of the first body and the third tip region of the second body.   
     
     
         18 . An integrated circuit structure comprising:
 a first non-planar semiconductor device comprising
 a first source region and a first drain region, and 
 a first body laterally extending between the first source region and the first drain region, the first body comprising (i) a first core structure including a continuous section with a first end abutting the first source region and a second end abutting the first drain region, and (ii) a first peripheral structure wrapped around a middle section of the first core structure; and 
   a second non-planar semiconductor device comprising
 a second source region and a second drain region, and 
 a second body laterally extending between the second source region and the second drain region, the second body comprising (i) a second core structure including a continuous section with a first end abutting the second source region and a second end abutting the second drain region, and (ii) a second peripheral structure wrapped around a middle section of the second core structure, 
   wherein the first peripheral structure is compositionally different from the second peripheral structure.   
     
     
         19 . The integrated circuit structure of  claim 18 , wherein the first peripheral structure is compositionally different from the first core structure, and wherein the second peripheral structure is compositionally different from the second core structure. 
     
     
         20 . The integrated circuit structure of  claim 18 , wherein:
 the first and second core structures comprises group IV semiconductor material; and   at least one of the first or second peripheral structures comprises group III-IV semiconductor material.