TSV Coupled Integrated Circuits and Methods

Abstract

According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

What is claimed is: 
     
         1 . A method comprising:
 fabricating a memory macro unit;   forming a through silicon via (TSV); and   bonding the TSV at least partially through the fabricated memory macro unit.   
     
     
         2 . The method of  claim 1 , wherein forming the TSV comprises:
 etching a TSV trench from a substrate;   filling the TSV trench with copper; and   fabricating a back-end-of-line (BEOL) wiring for coupling to the TSV.   
     
     
         3 . The method of  claim 2 , further comprising:
 removing a layer from a back portion of the substrate to reveal the TSV.   
     
     
         4 . The method of  claim 2 , wherein bonding the TSV comprises:
 adjoining the TSV to the back-end-of-line (BEOL) stack, and coupling the BEOL stack to a face-to-face semiconductor wafer bond.   
     
     
         5 . The method of  claim 1 , further comprising:
 bonding the TSV vertically through and perpendicular to the memory macro unit.   
     
     
         6 . The method of  claim 5 , wherein the memory macro unit comprises:
 one or more word-line decoder blocks;   one or more memory arrays coupled to the one or more word-line decoder blocks;   control circuitry coupled to the one or more word-line decoder blocks and the one or more memory arrays; and   respective input/output (I/O) circuitry for each of the one or more memory arrays, wherein each of the I/O circuitry comprises sense amplifier circuitry, a pre-charge circuit, a column multiplexer, and input and output latches.   
     
     
         7 . The method of  claim 6 , wherein each of the I/O circuitry comprises sense amplifier circuitry, a pre-charge circuit, a column multiplexer, and input and output latches 
     
     
         8 . The method of  claim 5 , wherein the TSV comprises one or more TSVs, and further comprising:
 respectively bonding each of the one or more TSVs adjacent to one or more word-line driver circuitry and a word-line pre-decoding circuitry of the word-line decoder circuitry.   
     
     
         9 . The method of  claim 5 , wherein the TSV comprises one or more TSVs, and wherein the one or more TSVs are configured to transmit power, ground, I/O signals, or address pre-decoding signals. 
     
     
         10 . The method of  claim 5 , wherein the TSV comprises one or more TSVs, and further comprising:
 bonding a first TSV of the one or more TSVs vertically through a region adjacent to a first I/O circuitry and the control circuitry; and   bonding a second TSV of the one or more TSVs vertically through a region adjacent to a second I/O circuitry and the control circuitry.   
     
     
         11 . The method of  claim 5 , further comprising:
 bonding the TSV vertically through a region adjacent to a word-line decoder circuitry and a control circuitry.   
     
     
         12 . The method of  claim 11 , wherein the TSV comprises one or more TSVs, and wherein the one or more TSVs are configured to route global signals comprising: external clock signals, internal memory clock signals, pre-decoded address signals, memory bank read output signals, or memory bank write input signals. 
     
     
         13 . The method of  claim 6 ,
 wherein the TSV comprises one or more TSVs, and   wherein the one or more word-line decoder block comprises first and second word-line decoder blocks, and further comprising:
 bonding a first TSV of the one or more TSVs i vertically through a region adjacent to a first I/O circuitry and the control circuitry; 
 bonding a second TSV of the one or more TSVs vertically through a region adjacent to a second I/O circuitry and the control circuitry; 
 bonding a third TSV of the one or more TSVs vertically through a region adjacent to the first word-line decoder circuitry and the control circuit, and 
 bonding a fourth TSV of the one or more TSVs is bonded vertically through a region adjacent to the second word-line decoder circuitry and the control circuit. 
   
     
     
         14 . The method of  claim 6 , wherein each of the one or more memory arrays comprise first and second break cells, and wherein each of the first and second break cells are configured to divide each of the two or more memory arrays into first and second portions. 
     
     
         15 . The method of  claim 6 , wherein the TSV comprises one or more TSVs, and further comprising:
 bonding the one or more TSVs vertically through the memory arrays vertically and adjacent to the first and second break cells.   
     
     
         16 . The method of  claim 1 , further comprising:
 fabricating a second memory macro unit, and   bonding the TSV at least partially through the fabricated second memory macro unit.   
     
     
         17 . The method of  claim 1 , further comprising:
 folding the memory macro unit on two or more tiers.   
     
     
         18 . The method of  claim 1 , further comprising:
 forming an integrated circuit through face-to-face wafer stacking, face-to-back wafer stacking, or monolithic 3D integration.   
     
     
         19 . A computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including:
 receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs);   determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and   determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.   
     
     
         20 . The computer-readable storage medium of  claim 19 , further comprising:
 generating an output based on the one or more optimized TSV positionings; and   providing the output to an integrated circuit design tool.