Memory device with charge-recycling arrangement and method of operating the same

Abstract

A method (for recycling charge from a first bit line of a memory device to a second bit line of the memory device) includes: before pre-filling the second bit line, momentarily closing switches to transfer a first charge from the first bit line which is involved in a first read operation to the second bit line which is involved subsequently in a second read operation; and each of the first bit line and the second bit line being served by a same sense amplifier.

What is claimed is: 
     
         1 . A method for recycling charge from a first bit line of a memory device to a second bit line of the memory device, the method comprising:
 before pre-filling the second bit line, momentarily closing switches to transfer a first charge from the first bit line which is involved in a first read operation to the second bit line which is involved subsequently in a second read operation; and   each of the first bit line and the second bit line being served by a same sense amplifier.   
     
     
         2 . The method of  claim 1 , wherein:
 each of the first bit line and the second bit line is selectively connectable to the sense amplifier via a first branched line; and   the momentarily closing switches to transfer a first charge includes:
 recovering the first charge from the first bit line associated with a first memory cell of the memory device, the first charge being a residual of a preceding first evaluation included as a phase in the first read operation, the first evaluation being performed by the sense amplifier; 
 storing the first charge; 
 reusing the first charge to at least partially charge the first branched line; 
 supplementally pre-filling the first branched line to a reference charge; and 
   using the sense amplifier to make a second evaluation of a stored value in a second memory cell relative to the reference charge, the second evaluation being included in the second read operation.   
     
     
         3 . The method of  claim 2 , wherein the recovering includes:
 connecting the first bit line to the branched line to form a line pair;   connecting a capacitor to the line pair; and   transferring the first charge from the line pair into the capacitor.   
     
     
         4 . The method of  claim 3 , wherein:
 the transferring leaves a residual amount of charge (residual charge) on the line pair; and   the recovering further includes:
 disconnecting the line pair from the capacitor; and 
 reducing the residual charge on the line pair. 
   
     
     
         5 . The method of  claim 4 , wherein the reducing includes:
 connecting the line pair directly to ground.   
     
     
         6 . The method of  claim 2 , wherein:
 the recovering includes:
 storing the first charge in a capacitor; and 
   the reusing includes:
 connecting a second bit line to the branched line; and 
 transferring the first charge from the capacitor onto the branched line. 
   
     
     
         7 . The method of  claim 6 , wherein the supplementally pre-filling includes:
 disconnecting the branched line from the capacitor;   connecting the branched line to a corresponding one of first and second terminals of the sense amplifier; and   adjusting a charge-level on the branched line from the first charge to a reference charge.   
     
     
         8 . The method of  claim 7 , wherein the using the sense amplifier to make a second evaluation includes:
 connecting the branched line to the bit line to form a line pair and thereby producing a resultant charge; and   comparing the resultant charge against a reference signal at the sense amplifier.   
     
     
         9 . A memory device comprising:
 a first bit line;   a second bit line;   a branched line;   switches for selectively connecting the first bit line or the second bit line to the branched line; and   a controller configured to generate recycle control signals that control the switches to transfer a first charge via the branched line from the first bit line which is involved in a first read operation to a second bit line which is involved subsequently in a second read operation performed subsequently to the first read operation; and   each of the first bit line and the second bit line being served by a same sense amplifier.   
     
     
         10 . The memory device of  claim 9 , wherein the controller is further configured to generate recycle control signals that control the switches to do as follows including:
 recovering the first charge from a first bit line associated with a first memory cell, the first charge being a residual of a preceding first evaluation included as a phase in the first read operation, the first evaluation being performed by the sense amplifier; and   storing the first charge;   reusing the first charge to at least partially charge the branched line; and   supplementally pre-filling the first branched line to a reference charge; and   wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference charge, the second evaluation being included in the second read operation.   
     
     
         11 . The memory device of  claim 10 , wherein the controller is further configured to generate recycle control signals that control the switches to do as follows including:
 permitting, during the recovering, flow of charge (charge-flow) from the branched line to a capacitor to accumulate the first charge;   interrupting, during a drainage phase in which the first charge is preserved, charge-flow from the branched line to the capacitor; and   permitting, during the reusing, charge-flow from the capacitor to the branched line.   
     
     
         12 . The memory device of  claim 11 , wherein:
 the branched line is selectively connectable to a first terminal of the sense amplifier;   during the reusing, the controller is further configured to generate recycle control signals that control the switches to do as follows including:
 disconnecting the first terminal of the sense amplifier from the branched line; 
 connecting a selected one of the bit lines to the branched line to form a line pair; 
 permitting charge-flow between from the capacitor to the line pair. 
   
     
     
         13 . The memory device of  claim 10 , further comprising:
 a capacitor; and   a recycle switch, a first terminal of the recycle switch being connected to a first terminal of the capacitor, and a second terminal of the recycle switch being connected to the branched line, and a control terminal of the recycle switch being connected so as to receive control signals from the controller.   
     
     
         14 . A method of reading a memory device, the method comprising:
 recovering a first charge from a first bit line associated with a first memory cell that was a subject of a preceding first evaluation, the first evaluation being included as a phase in a first read operation, the first evaluation being performed by a sense amplifier;   reusing the first charge to at least partially charge a branched line;   supplementally pre-filling the branched line to a reference charge; and   using the sense amplifier to make a second evaluation of evaluating a stored value in a second memory cell based on a resultant charge,
 the resultant charge resulting from a combination of the reference charge on the branched line and a data charge on a second bit line associated with a second memory cell of the memory device; and 
 the second evaluation being included in a second read operation. 
   
     
     
         15 . The method of  claim 14 , wherein the recovering the first charge includes:
 connecting the first bit line to the branched line to form a line pair;   connecting a capacitor to the line pair; and   transferring the first charge from the line pair into the capacitor.   
     
     
         16 . The method of  claim 15 , wherein:
 the transferring leaves a residual amount of charge (residual charge) on the line pair; and   after the transferring, the method further comprises:
 disconnecting the line pair from the capacitor; and 
 reducing the residual charge on the line pair. 
   
     
     
         17 . The method of  claim 16 , wherein the reducing includes:
 connecting the line pair directly to ground.   
     
     
         18 . The method of  claim 14 , wherein:
 the recovering recovers the first charge into a capacitor; and   the reusing includes:
 connecting the second bit line to the branched line; and 
 transferring the first charge from a capacitor onto the branched line. 
   
     
     
         19 . The method of  claim 18 , wherein the supplementally pre-filling includes:
 disconnecting the branched line from a capacitor;   connecting the branched line to a corresponding one of first and second terminals of the sense amplifier; and   adjusting a charge-level on the branched line from the first charge to the reference charge.   
     
     
         20 . The method of  claim 19 , wherein the evaluating includes:
 connecting the branched line to the bit line to form a line pair and thereby producing the resultant charge; and   comparing the resultant charge against a reference signal at the sense amplifier.