Enabling device security by design enumeration selective targeting

Abstract

A computer-implemented method of ensuring integrity of an integrated circuit (IC) is provided. The computer-implemented method includes providing a design layer that meets design rule checks (DRCs), identifying a first critical dimension (CD) distribution of the design layer and using retargeting shapes in the design layer to enable a biasing of CDs of targets to enable a provision of two different CD distributions, which are DRC clean and which are separate from one another and which cannot be expressed by a single Gaussian distribution.

What is claimed is: 
     
         1 . A computer-implemented method of ensuring integrity of an integrated circuit (IC), the computer-implemented method comprising:
 providing a design layer that meets design rule checks (DRCs);   identifying a first critical dimension (CD) distribution of the design layer; and   using retargeting shapes in the design layer to enable a biasing of CDs of targets to enable a provision of two different CD distributions, which are DRC clean and which are separate from one another and which cannot be expressed by a single Gaussian distribution.   
     
     
         2 . The computer-implemented method according to  claim 1 , wherein the two different CD distributions are controllably non-Gaussian. 
     
     
         3 . The computer-implemented method according to  claim 1 , wherein the using of the retargeting shapes comprises using retargeting shapes from randomized locations. 
     
     
         4 . The computer-implemented method according to  claim 1 , wherein the using of the retargeting shapes comprises randomly resizing the retargeting shapes. 
     
     
         5 . A computer-implemented method of designing semiconductor chip layers, the computer-implemented method comprising:
 designing semiconductor chip layers that meet design rule checks (DRCs) to form a device with a characteristic property; and   enumerating objects of the device to assign a retargeting operation to respective locations of each of the objects to adjust the characteristic property.   
     
     
         6 . The computer-implemented method according to  claim 5 , further comprising:
 confirming that the retargeting operation meets the DRCs; and   executing the retargeting operation in an event the retargeting operation meets the DRCs.   
     
     
         7 . The computer-implemented method according to  claim 6 , wherein the executing of the retargeting operation comprises respectively upsizing, downsizing or moving each of the objects. 
     
     
         8 . The computer-implemented method according to  claim 5 , wherein the characteristic property comprises a critical dimension (CD) of the device and an adjustment of the characteristic property results in a provision of two different CD distributions that are separate from one another and cannot be expressed by a single Gaussian distribution. 
     
     
         9 . The computer-implemented method according to  claim 8 , wherein the device has a unique signature following the adjustment of the characteristic property. 
     
     
         10 . The computer-implemented method according to  claim 9 , wherein the device comprises an array of elements and each of the objects is a corresponding one of the elements. 
     
     
         11 . The computer-implemented method according to  claim 10 , wherein the respective locations of each of the objects are randomized within the array. 
     
     
         12 . The computer-implemented method according to  claim 10 , wherein the device is one or more of an arbiter, a ring oscillator, read-access-memory (RAM), a flip-flop and a latch. 
     
     
         13 . The computer-implemented method according to  claim 10 , wherein:
 the characteristic property comprises a distribution of resistances inherent to process variation of each of the elements, and   an adjustment of the characteristic property comprises modifying one or more of the elements to change the distribution of resistances.   
     
     
         14 . The computer-implemented method according to  claim 13 , wherein the distribution of resistances is uni-modal prior to the adjustment of the characteristic property and at least bi-modal following the adjustment of the characteristic property. 
     
     
         15 . A semiconductor chip, comprising:
 a grid; and   an array of elements electrically coupled to the grid according to a design that meets design rule checks (DRCs) to form a device,   the array of elements forming a device and comprising a first group of elements having similar physical characteristics and a second group of elements having physical characteristics that differ from those of the first group of elements such that the device has two different critical dimension (CD) distributions that are separate and that cannot be described by a single Gaussian expression.   
     
     
         16 . The semiconductor chip according to  claim 15 , wherein the device is one or more of an arbiter, a ring oscillator, read-access-memory (RAM), a flip-flop and a latch. 
     
     
         17 . The semiconductor chip according to  claim 15 , wherein elements of the second group of elements are randomly located in the array of elements. 
     
     
         18 . The semiconductor chip according to  claim 15 , wherein the elements of the array of elements are resistive elements and the second group of elements are upsized, downsized or moved relative to the first group of elements. 
     
     
         19 . The semiconductor chip according to  claim 18 , wherein each of the two different CD distributions is a distribution of resistances inherent to process variation of each of the elements of the array of elements. 
     
     
         20 . The semiconductor chip according to  claim 18 , wherein the two different CD distribution are at least bi-modal.