Amplifier with adaptive biasing

Abstract

An amplifier circuit includes an amplifier, a resistor, and an adaptive bias circuit. The amplifier includes an output and a tail input. The amplifier is configured to generate an output signal representative of a difference of a first input signal and a second input signal. The resistor is coupled to the output of the amplifier. The resistor is configured to lower an output resistance of the amplifier. The adaptive bias circuit is coupled between the output of the amplifier and the tail input of the amplifier. The adaptive bias circuit is configured to generate a detection current based on the output signal, and provide the detection current to the tail input of the amplifier to increase the gain of the amplifier based on the output signal.

What is claimed is: 
     
         1 . An amplifier circuit, comprising:
 an amplifier including:
 an output; and 
 a tail input; 
   a power supply terminal;   a resistor coupled between the power supply terminal and the output of the amplifier;   an adaptive bias circuit including:
 a source degenerated detector circuit including:
 an input coupled to the output of the amplifier; and 
 an output; and 
 
 a source degenerated current mirror circuit including:
 an input coupled to the output of the source degenerated detector circuit; and 
 an output coupled to the tail input of the amplifier. 
 
   
     
     
         2 . The amplifier circuit of  claim 1 , wherein:
 the resistor is a first resistor; and   the source degenerated detector circuit includes:
 a transistor including:
 a control terminal coupled to the output of the amplifier; 
 a first current terminal coupled to the input of the source degenerated current mirror circuit; and 
 a second current terminal; and 
 
 a second resistor coupled between the second current terminal and the power supply terminal. 
   
     
     
         3 . The amplifier circuit of  claim 2 , wherein:
 the transistor is a first transistor; and   the source degenerated current mirror circuit includes:
 a second transistor including:
 a first current terminal coupled to the first current terminal of the first transistor; 
 a control terminal coupled to the first current terminal of the first transistor; and 
 a second current terminal; 
 
 a third resistor coupled between the second current terminal of the second transistor and a ground terminal; 
 a third transistor including:
 a first current terminal coupled to the tail input of the amplifier; 
 a control terminal coupled to the first current terminal of the first transistor; and 
 a second current terminal; and 
 a fourth resistor coupled between the second current terminal of the third transistor and the ground terminal. 
 
   
     
     
         4 . The amplifier circuit of  claim 3 , wherein the source degenerated current mirror circuit includes a capacitor coupled between the control terminal of the second transistor and the ground terminal. 
     
     
         5 . The amplifier circuit of  claim 3 , wherein a gain boost provided to the amplifier by the adaptive bias circuit is a ratio of a resistance of the first resistor to a resistance of the second resistor. 
     
     
         6 . The amplifier circuit of  claim 1 , further comprising:
 a transistor coupled between the power supply terminal and the resistor, and including:
 a first current terminal coupled to the power supply terminal; 
 a second current terminal coupled to the resistor; and 
 a control terminal coupled to the second current terminal. 
   
     
     
         7 . The amplifier circuit of  claim 6 , wherein:
 the transistor is a first transistor; and   the amplifier circuit includes a second transistor connected as a diode, and coupled in series with the first transistor.   
     
     
         8 . The amplifier circuit of  claim 1 , wherein the amplifier includes:
 a first signal input;   a second signal input;   a first current source;   a second current source;   a first transistor including:
 a first current terminal coupled to the first current source; 
 a second current terminal coupled to the second current source; and 
 a control terminal coupled to the first signal input; and 
   a second transistor including:
 a first current terminal coupled to the first current source and the input of the source degenerated detector circuit; 
 a second current terminal coupled to the second current source and the output of the source degenerated current mirror circuit; and 
 a control terminal coupled to the second signal input. 
   
     
     
         9 . An amplifier circuit, comprising:
 an amplifier including an output and a tail input, and configured to generate an output signal representative of a difference of a first input signal and a second input signal;   a resistor coupled to the output of the amplifier, and configured to lower an output resistance of the amplifier; and   an adaptive bias circuit coupled between the output of the amplifier and the tail input of the amplifier, and configured to:
 generate a detection current based on the output signal; and 
 provide the detection current to the tail input of the amplifier to increase a gain of the amplifier based on the output signal. 
   
     
     
         10 . The amplifier circuit of  claim 9 , further comprising a diode-connected transistor configured to pass a current to the output of the amplifier through the resistor. 
     
     
         11 . The amplifier circuit of  claim 10 , wherein:
 the diode-connected transistor is a first diode-connected transistor; and   the amplifier circuit includes a second diode-connected transistor coupled in series with the first diode-connected transistor.   
     
     
         12 . The amplifier circuit of  claim 9 , wherein the adaptive bias circuit includes a source degenerated detector circuit configured to generate the detection current based on the output signal. 
     
     
         13 . The amplifier circuit of  claim 12 , wherein the adaptive bias circuit includes a source degenerated current mirror circuit coupled to the source degenerated detector circuit and the tail input, and configured to mirror the detection current to the tail input of the amplifier. 
     
     
         14 . The amplifier circuit of  claim 13 , wherein:
 the resistor is a first resistor; and   the source degenerated detector circuit includes:
 a first transistor; and 
 a second resistor coupled to a source of the first transistor; 
   the source degenerated current mirror circuit includes:
 a diode-connected transistor including a drain and a gate coupled to a drain of the first transistor; 
 a third resistor coupled to a source of the diode-connected transistor; 
 a second transistor including:
 a gate coupled to the drain of the first transistor; and 
 a drain coupled to the tail input of the amplifier; and 
 
 a fourth resistor coupled to a source of the second transistor. 
   
     
     
         15 . The amplifier circuit of  claim 14 , wherein a gain boost provided to the amplifier by the adaptive bias circuit is a ratio of a resistance of the first resistor to a resistance of the second resistor. 
     
     
         16 . The amplifier circuit of  claim 9 , wherein the adaptive bias circuit is configured increase a tail current flowing through the amplifier based on an increase in amplitude of the output signal of the amplifier. 
     
     
         17 . A voltage regulator circuit, comprising:
 an output terminal adapted to be coupled to a load circuit;   an error amplifier including an output and a tail input, and configured to generate an error signal representative of a difference of an output voltage and a reference voltage;   a load resistor coupled to the output of the error amplifier, and configured to lower an output resistance of the error amplifier;   an adaptive bias circuit coupled between the output of the error amplifier and the tail input of the error amplifier, and configured to:
 generate a detection current based on the error signal; and 
 provide the detection current to the tail input of the error amplifier to increase a gain of the error amplifier based on the error signal, and 
   a pass transistor coupled to the output of the error amplifier and the output terminal, and configured to pass a current to the output terminal responsive to the error signal.   
     
     
         18 . The voltage regulator circuit of  claim 17 , wherein the adaptive bias circuit includes a source degenerated detector circuit configured to generate the detection current based on the error signal. 
     
     
         19 . The voltage regulator circuit of  claim 17 , wherein the adaptive bias circuit includes a source degenerated current mirror circuit coupled to the source degenerated detector circuit and the tail input, and configured to mirror the detection current to the tail input of the error amplifier. 
     
     
         20 . The voltage regulator circuit of  claim 19  wherein:
 the source degenerated detector circuit includes a first degeneration resistor having a first resistance; 
 the source degenerated current mirror circuit includes:
 a second degeneration resistor having approximately the first resistance; and 
 a third degeneration resistor have approximately the first resistance; 
 
 the load resistor has a second resistance; and 
 a gain boost provided to the error amplifier by the adaptive bias circuit is a ratio of the second resistance to the first resistance.