Semiconductor device, memory system and semiconductor memory device

Abstract

A semiconductor device includes a transmission and reception circuit and a control circuit. The transmission and reception circuit transmits and receives a signal to and from a semiconductor memory device. The control circuit acquires threshold voltage distribution information of a memory element connected to a word line for read disturb detection to which a second voltage higher than a first voltage applied to an adjacent word line adjacent to a read target word line during a read operation is applied and determines an influence of read disturb based on the threshold voltage distribution information.

1 - 18 . (canceled) 
     
     
         19 . A memory system comprising:
 a nonvolatile memory including a plurality of blocks, the plurality of blocks including at least a first block, each of the plurality of blocks being a unit of a data erase operation and including a plurality of word lines, the plurality of word lines including at least a first word line, a second word line, and a third word line, each of the plurality of word lines connecting a plurality of memory cells, each of the plurality of memory cells being configured to store data in accordance with a threshold voltage thereof; and   a controller electrically connected to the nonvolatile memory and configured to, in performing a first read operation on the first block, instruct the nonvolatile memory to:
 apply a first voltage to the first word line of the first block to determine whether the threshold voltage of at least one of the plurality of memory cells connected to the first word line is higher than the first voltage or not; 
 apply a second voltage to the second word line of the first block, the second voltage being a voltage that turns on the plurality of memory cells connected to the second word line regardless of data stored therein; and 
 apply a third voltage to the third word line of the first block, the third voltage being higher than the second voltage, wherein 
   the controller is further configured to:
 in response to determining that the number of memory cells connected to the third word line whose threshold voltage is higher than a first threshold voltage is larger than a first value, determine to perform a refresh operation on the first block. 
   
     
     
         20 . The memory system according to  claim 19 , wherein
 the first threshold voltage being a voltage to determine whether at least one of the plurality of memory cells connected to the third word line is in an erased state or not.   
     
     
         21 . The memory system according to  claim 19 , wherein
 the controller is configured to:
 in response to determining that the number of erased memory cells connected to the third word line is larger than the first value, determine to perform the refresh operation on the first block. 
   
     
     
         22 . The memory system according to  claim 19 , wherein
 the controller is configured to:
 by sending a first command to the nonvolatile memory, acquire, from the nonvolatile memory, the number of memory cells connected to the third word line whose threshold voltage is higher than the first threshold voltage. 
   
     
     
         23 . The memory system according to  claim 19 , wherein
 the plurality of blocks further includes a second block different from the first block, and   the controller is configured to:   in performing the refresh operation on the first block, read data from the first block and write the read data to the second block.   
     
     
         24 . The memory system according to  claim 19 , wherein
 the controller is further configured to:
 not to write data received from a host to any of the plurality of memory cells connected to the third word line; and 
 write dummy data to at least one of the plurality of memory cells connected to the third word line before performing the first read operation on the first block. 
   
     
     
         25 . The memory system according to  claim 19 , wherein
 the controller is further configured to:   after performing the first read operation on the first block,
 instruct the nonvolatile memory to perform the data erase operation on the first block; and 
 in performing a second read operation on the first block after the data erase operation, instruct the nonvolatile memory to, apply a fourth voltage to the third word line of the first block, the fourth voltage being higher than the second voltage. 
   
     
     
         26 . The memory system according to  claim 19 , wherein
 the controller is configured to, in performing the first read operation on the first block, instruct the nonvolatile memory to:
 apply the second voltage to the second word line in first times; and 
 apply the third voltage to the third word line in second times, the second times being larger than the first times. 
   
     
     
         27 . The memory system according to  claim 19 , wherein
 the controller is configured to, in performing the first read operation on the first block, instruct the nonvolatile memory to apply the third voltage to the third word line in a plurality of times.   
     
     
         28 . The memory system according to  claim 19 , wherein
 the controller is configured to, in performing the first read operation on the first block, further instruct the nonvolatile memory to:
 apply the second voltage to the second word line for a first period; and 
 apply the third voltage to the third word line for a second period, the second period being longer than the first period. 
   
     
     
         29 . A memory system comprising:
 a nonvolatile memory including a plurality of blocks, the plurality of blocks including at least a first block, each of the plurality of blocks being a unit of a data erase operation and including a plurality of word lines, the plurality of word lines including at least a first word line, a second word line, and a third word line, each of the plurality of word lines connecting a plurality of memory cells, each of the plurality of memory cells being configured to store data in accordance with a threshold voltage thereof; and   a controller electrically connected to the nonvolatile memory and configured to, in performing a first read operation on the first block, instruct the nonvolatile memory to:
 apply a first voltage to the first word line of the first block to determine whether the threshold voltage of at least one of the plurality of memory cells connected to the first word line is higher than the first voltage or not; 
 apply a second voltage to the second word line of the first block in first times, the second voltage being a voltage that turns on the plurality of memory cells connected to the second word line regardless of data stored therein; and 
 apply a third voltage to the third word line of the first block in second times, the third voltage being higher than the second voltage, the second times being larger than the first times. 
   
     
     
         30 . The memory system according to  claim 29 , wherein
 the controller is configured to:   use at least one of the plurality of memory cells connected to the third word line to estimate an amount of read disturb on the first block.   
     
     
         31 . The memory system according to  claim 30 , wherein
 the controller is configured to:   estimate the amount of read disturb on the first block on the basis of the number of memory cells connected to the third word line whose threshold voltage is higher than a first threshold voltage.   
     
     
         32 . The memory system according to  claim 30 , wherein
 the controller is configured to:   estimate the amount of read disturb on the first block on the basis of the number of erased memory cells connected to the third word line.   
     
     
         33 . The memory system according to  claim 30 , wherein
 the controller is configured to:   in response to determining that the amount of read disturb on the first block is higher than a first threshold, determine to perform a refresh process on the first block.   
     
     
         34 . The memory system according to  claim 33 , wherein
 the plurality of blocks further includes a second block different from the first block, and   the controller is configured to:   in performing the refresh operation on the first block, read data from the first block and write the read data to the second block.   
     
     
         35 . The memory system according to  claim 29 , wherein
 the controller is further configured to:
 not to write data received from a host to any of the plurality of memory cells connected to the third word line; and 
 write dummy data to at least one of the plurality of memory cells connected to the third word line before performing the first read operation on the first block. 
   
     
     
         36 . The memory system according to  claim 29 , wherein
 the controller is further configured to:   after performing the first read operation on the first block,
 instruct the nonvolatile memory to perform the data erase operation on the first block; and 
 in performing a second read operation on the first block after the data erase operation, instruct the nonvolatile memory to, apply a fourth voltage to the third word line of the first block, the fourth voltage being higher than the second voltage. 
   
     
     
         37 . The memory system according to  claim 29 , wherein
 the controller is configured to, in performing the first read operation on the first block, instruct the nonvolatile memory to apply the third voltage to the third word line in a plurality of times.   
     
     
         38 . The memory system according to  claim 29 , wherein
 the controller is configured to, in performing the first read operation on the first block, further instruct the nonvolatile memory to:
 apply the second voltage to the second word line for a first period in each of the first times; and 
 apply the third voltage to the third word line for a second period in each of the second times, the second period being longer than the first period.