Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, a bitline, a bitline contact and a land pad. The bitline is over the substrate. The bitline contact is in contact with a bottom of the bitline and in the substrate. The bitline contact includes a first portion and a second portion below the first portion, and the first portion is wider than the second portion from a cross-section view. A word line is adjacent to the bitline contact. A land pad is on the substrate, and the land pad is adjacent to the word line, such that the word line is between the bitline contact and the land pad.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a bitline over the substrate;   a bitline contact in contact with a bottom of the bitline and in the substrate, wherein the bitline contact comprises a first portion and a second portion below the first portion, the first portion is wider than the second portion in a cross-section view;   a word line adjacent to the bitline contact; and   a land pad on the substrate, wherein the land pad is adjacent to the word line, such that the word line is between the bitline contact and the land pad.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a cross-section contour of the first portion of the bitline contact and a cross-section contour of the second portion of the bitline contact are discontinuous. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first portion of the bitline contact has a sidewall, a top of the sidewall of the first portion of the bitline contact is connected to the bitline, a bottom of the sidewall of the first portion of the bitline contact is connected to the second portion of the bitline contact, and the top of the sidewall of the first portion of the bitline contact is straighter than the bottom of the sidewall of the first portion of the bitline contact. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the second portion of the bitline contact has a sidewall connected to the bottom of the sidewall of the first portion of the bitline contact, and the sidewall of the second portion of the bitline contact is straighter than the bottom of the sidewall of the first portion of the bitline contact. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a sidewall of the first portion of the bitline contact is substantially aligned with a sidewall of the bitline. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the bitline contact comprises silicon and a dopant, the dopant has a smaller atomic radius than silicon. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a dielectric structure in the substrate and adjacent to the land pad. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a capacitor connected with the land pad. 
     
     
         9 . The semiconductor device of  claim 1 , wherein a width of the first portion of the bitline contact is in a range from 470 angstrom to 530 angstrom, and a width of the second portion of the bitline contact is in a range from 380 angstrom to 420 angstrom. 
     
     
         10 . The semiconductor device of  claim 1 , wherein a depth of the first portion of the bitline contact is in a range from 160 angstrom to 200 angstrom, and a depth of the second portion of the bitline contact is in a range from 400 angstrom to 440 angstrom. 
     
     
         11 . A method of forming a semiconductor device, comprising:
 forming a first photoresist layer on a substrate, wherein the first photoresist layer has an opening exposing a portion of the substrate;   forming an implant region in the portion of the substrate by implanting a first dopant into the substrate by using the first photoresist layer as a mask;   removing the first photoresist layer over the substrate;   forming a second photoresist layer over the substrate, wherein the second photoresist layer partially covers the implant region;   performing a first etching process to remove the implant region such that a recess is formed in the substrate;   performing a second etching process to remove a portion of the substrate to form a trench in the substrate, wherein the trench is narrower than the recess in the substrate; and   depositing a semiconductive material in the recess and the trench to form a bitline contact in the substrate.   
     
     
         12 . The method of  claim 11 , further comprising doping a second dopant into the semiconductive material after depositing the semiconductive material in the recess and the trench. 
     
     
         13 . The method of  claim 12 , wherein the second dopant has a smaller atomic radius than the semiconductive material. 
     
     
         14 . The method of  claim 11 , wherein the first dopant is an n-type dopant. 
     
     
         15 . The method of  claim 11 , further comprising planarizing the semiconductive material in the recess after depositing the semiconductive material in the recess and the trench. 
     
     
         16 . The method of  claim 11 , further comprising adjusting an implantation dosage when forming the implant region in the portion of the substrate to control a depth of the recess. 
     
     
         17 . The method of  claim 11 , further comprising adjusting an implantation energy when forming the implant region in the portion of the substrate to control a depth of the recess. 
     
     
         18 . The method of  claim 11 , wherein performing the first etching process is such that a portion of the second photoresist layer is suspended over the recess in the substrate.