Via Structures

Abstract

A semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device includes a source via electrically coupled to the source feature and a drain via electrically coupled to the drain feature. The semiconductor device includes a source via metal line disposed over and directly connected to the source via. The semiconductor device includes and a drain via metal line disposed over and directly connected to the drain via. The source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view. The drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from a top view.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a source feature and a drain feature disposed over a substrate;   a source via electrically coupled to the source feature;   a drain via electrically coupled to the drain feature,   a source via metal line disposed over and directly connected to the source via; and   a drain via metal line disposed over and directly connected to the drain via,   wherein the source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view, and wherein the drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from the top view.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a source contact between the source via and the source feature; and   a drain contact between the drain via and the drain feature,   wherein at least one sidewall of the source via extends past a sidewall of the source contact along the first direction.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the source via and the source contact has a first contact surface area, the drain via and the drain contact has a second contact surface area, and the first contact surface area is greater than the second contact surface area. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the source via has a first length along the first direction, the drain via has a second length along the first direction, and a ratio of the first length to the second length is about 1.1:1 to about 12:1. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first length is in a range between about 3 nm and about 300 nm, and the second length is in a range between about 3 nm and about 60 nm. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the source via has a greater length than the drain via along the first direction, wherein the source via has about the same width as the drain via along a second direction perpendicular to the first direction. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a gate structure extending over the substrate along the first direction;   a gate via electrically coupled to the gate structure; and   a gate metal line disposed over and directly connected to the gate via,   wherein the gate metal line has outer edges extending lengthwise along the first direction and the outer edges of the gate metal line are offset from edges of the gate via from a top view.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the gate metal line and the drain via metal line have a same width along the first direction. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the gate metal line has a first metal line width along the first direction, the source via metal line has a second metal line width along the first direction, and the second metal line width is greater than the first metal line width. 
     
     
         10 . A semiconductor device, comprising:
 source features and drain features disposed over a substrate;   source contacts and drain contacts disposed over the source features and drain features, respectively;   source vias disposed over the source contacts, wherein the source vias and the source contacts have first contact surface areas;   drain vias disposed over the drain contacts, wherein the drain vias and the drain contacts have second contact surface areas, wherein each of the first contact surface areas is greater than each of the second contact surface areas   a source via metal line having a width along a first direction, the source via metal line contacting multiple source vias by extending lengthwise along a second direction perpendicular to the first direction; and   a drain via metal line having a width along the first direction, the drain via metal line contacting multiple drain vias by extending lengthwise along the second direction.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the width of the source via metal line is greater than the width of the drain via metal line. 
     
     
         12 . The semiconductor device of  claim 11 , wherein a ratio between the width of the source via metal line to the width of the drain via metal line is between 1 to 30. 
     
     
         13 . The semiconductor device of  claim 10 , wherein each of the source vias have a greater length than each of the drain vias along the first direction, and each of the source vias have about the same width as each of the drain vias along the second direction. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the multiple source vias include source vias having different lengths along the first direction. 
     
     
         15 . The semiconductor device of  claim 14 ,
 wherein one of the multiple source vias have first outer edges extending along the second direction, and the outer edges are substantially aligned to edges of the source via metal line from a top view,   wherein another one of the multiple source vias have second outer edges extending along the second direction, wherein one of the second outer edges is offset from edges of the source via metal line from the top view.   
     
     
         16 . The semiconductor device of  claim 10 , wherein the source vias include extended source vias that extend beyond the source contacts along the first direction. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the extended source vias have extended portions that directly contact an interlayer dielectric (ILD) layer disposed over the substrate. 
     
     
         18 . A semiconductor device, comprising:
 a source feature and a drain feature disposed over a substrate;   a source contact and a drain contact landing on the source feature and the drain feature, respectively;   a source via and a drain via landing on the source contact and the drain contact, respectively; and   a source via metal line and a drain via metal line disposed over and directly connected to the source via and the drain via, respectively,   wherein the source via is larger than the drain via,   wherein along a first direction, a portion of the source contact extends beyond an outer edge of the source feature, a portion of the source via extends beyond an outer edge of the source contact, and a portion of the source via metal line extends beyond an outer edge of the source via.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the source via metal line has a first width along the first direction, the drain via metal line has a second width along the first direction, and the first width is greater than the second width. 
     
     
         20 . The semiconductor device of  claim 18 , wherein along the first direction, the drain contact extends between outer edges of the drain feature, and the drain via extends between outer edges of the drain contact.