Deep neural network

Abstract

A hardware neural network system includes an input buffer for input neurons (Nbin), an output buffer for output neurons (Nbout), and a third buffer for synaptic weights (SB) connected to a Neural Functional Unit (NFU) and a control logic (CP) for performing synapses and neurons computations. The NFU pipelines a computation into stages, the stages including weight blocks (WB), an adder tree, and a non-linearity function.

What is claimed is: 
     
         1 . A hardware neural network system comprising:
 an input buffer for input neurons (Nbin);   an output buffer for output neurons (Nbout); and   a third buffer for synaptic weights (SB) connected to a Neural Functional Unit (NFU) and a control logic (CP) for performing synapses and neurons computations.   
     
     
         2 . The hardware neural network system of  claim 1  wherein the NFU pipelines a computation into stages. 
     
     
         3 . The hardware neural network system of  claim 2  wherein the stages comprise:
 weight blocks (WB); 
 an adder tree; and 
 a non-linearity function. 
 
     
     
         4 . A method comprising:
 mapping floating-point based Deep Neural Networks (DNNs) to 8-bit dynamic fixed-point networks with integer power-of-two weights with no change in network architecture, the 8-bit dynamic fixed-point DNNs enabling different radix points between layers.   
     
     
         5 . The method of  claim 4  wherein integer power-of-two weights enable a multiplier-free hardware accelerator design performing computation on dynamic fixed-point precision. 
     
     
         6 . A hardware accelerator comprising:
 memory subsystems used to store intermediate values and outputs and buffer inputs and weights, the memory systems comprising an SRAM buffer array, a DMA, and control logic responsible for ensuring that data is loaded into buffers and made available to a neural functional unit (NFU) at an appropriate clock cycle without additional latency.   
     
     
         7 . The hardware accelerator of  claim 6  wherein the NFU pipelines a computation into stages. 
     
     
         8 . The hardware accelerator of  claim 7  wherein the stages comprise:
 weight blocks (WB); 
 an adder tree; and 
 a non-linearity function.