Semiconductor device and method for driving the same

Abstract

Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first wiring electrically connected to a first gate of a first transistor;   a second wiring electrically connected to a second gate of the first transistor;   a third wiring electrically connected to one of a source and a drain of the first transistor; and   a fourth wiring electrically connected to the other of the source and the drain of the first transistor.   
     
     
         3 . A semiconductor device comprising:
 a first wiring electrically connected to a first gate of a first transistor;   a second wiring electrically connected to a second gate of the first transistor;   a third wiring electrically connected to one of a source and a drain of the first transistor; and   a fourth wiring electrically connected to the other of the source and the drain of the first transistor,   wherein the first gate of the first transistor is configured to function as a control gate, and   wherein the second gate of the first transistor is configured to function as a storage gate.   
     
     
         4 . A semiconductor device comprising:
 a first wiring electrically connected to a first gate of a first transistor, the first wiring being a word line;   a second wiring electrically connected to a second gate of the first transistor, the second wiring being a data line;   a third wiring electrically connected to one of a source and a drain of the first transistor; and   a fourth wiring electrically connected to the other of the source and the drain of the first transistor,   wherein the first gate of the first transistor is configured to be supplied with a first potential from the word line, and   wherein the second gate of the first transistor is configured to be supplied with a second potential from the data line.   
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein a channel formation region of the first transistor comprises a semiconductor layer, and   wherein the semiconductor layer overlaps with the first gate of the first transistor with the second gate of the first transistor provided therebetween.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein a channel formation region of the first transistor comprises a semiconductor layer, and   wherein the semiconductor layer overlaps with the first gate of the first transistor with the second gate of the first transistor provided therebetween.   
     
     
         7 . The semiconductor device according to  claim 4 ,
 wherein a channel formation region of the first transistor comprises a semiconductor layer, and   wherein the semiconductor layer overlaps with the first gate of the first transistor with the second gate of the first transistor provided therebetween.   
     
     
         8 . The semiconductor device according to  claim 2 ,
 wherein the first transistor comprises a third gate, and   wherein the third gate of the first transistor overlaps with the first gate of the first transistor and the second gate of the first transistor.   
     
     
         9 . The semiconductor device according to  claim 3 ,
 wherein the first transistor comprises a third gate, and   wherein the third gate of the first transistor overlaps with the first gate of the first transistor and the second gate of the first transistor.   
     
     
         10 . The semiconductor device according to  claim 4 ,
 wherein the first transistor comprises a third gate, and   wherein the third gate of the first transistor overlaps with the first gate of the first transistor and the second gate of the first transistor.