US2023133314A1PendingUtilityA1
Interface, electronic device, and communication system
Est. expiryJun 29, 2040(~13.9 yrs left)· nominal 20-yr term from priority
H04L 1/0064H04L 1/0078H04L 1/0041H04L 1/0057H04L 1/0052H04L 1/0061H04L 12/02G06F 13/4221H04L 1/0071H04L 1/0067H04L 1/0045H04L 1/004H04L 69/324H04L 1/0043H04L 1/0042
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Claims
Abstract
An interface includes a first functional part and a second functional part. The first functional part is configured to implement processing dependent on a medium access control (MAC) rate, and the second functional part is configured to implement processing independent of the MAC rate.
Claims
exact text as granted — not AI-modified1 . An interface, comprising:
a functional part 1; and a functional part 2; wherein the functional part 1 is configured to implement processing dependent on a medium access control (MAC) rate; and wherein the functional part 2 is configured to implement processing independent of the MAC rate.
2 . The interface according to claim 1 , wherein the interface is an Ethernet interface.
3 . The interface according to claim 1 , wherein the functional part 1 comprises a MAC module, a reconciliation sublayer (RS) module, and an encode and rate matching module at a physical coding sublayer (PCS).
4 . The interface according to claim 3 , wherein the functional part 2 comprises one or more functional units, wherein the one or more functional units comprise a first functional unit, and wherein the first functional unit comprises a transcode module, a scramble module, an alignment marker insertion module, a forward error correction (FEC) module, a physical medium attachment sublayer (PMA) module, and a physical medium dependent (PMD) module.
5 . The interface according to claim 3 , wherein the functional part 2 comprises one PMA/PMD module and one or more functional units, wherein the one or more functional units comprise a second functional unit, the second functional unit comprises a transcode module, a scramble module, an alignment marker insertion module, and a forward error correction FEC module, and the second functional unit is coupled to the PMA/PMD module.
6 . The interface according to claim 3 , wherein the functional part 2 comprises a first-level functional unit and a second-level functional unit that are concatenated;
wherein the first-level functional unit comprises one or more first-level subunits, and wherein at least one first-level subunit in the first-level functional unit comprises a transcode module, a scramble module, an alignment marker insertion module, a forward error correction (FEC) module, and a PMA module; and wherein the second-level functional unit comprises one or more second-level subunits, and wherein at least one second-level subunit in the second-level functional unit comprises a PCS/FEC/PMA module and a PMD module.
7 . The interface according to claim 4 , wherein data output by FEC modules of a plurality of functional parts 2 is interleaved at a PMA layer.
8 . The interface according to claim 6 , wherein the FEC module comprised in the at least one first-level subunit in the first-level functional unit is configured to perform Reed-Solomon (RS) ( 544 , 514 ) FEC encoding, and wherein the FEC module comprised in the at least one second-level subunit in the second-level functional units is configured to perform Bose-Chaudhuri-Hocquenghem (BCH) FEC, Reed-Solomon forward error correction (RS FEC), polar FEC, low density parity check forward error correction (LDPC FEC), concatenated forward error correction (CFEC), open forward error correction (OFEC), or Turbo product code forward error correction (TPC FEC).
9 . The interface according to claim 3 , wherein the interface comprises an optical digital signal processor (oDSP).
10 . The interface according to claim 3 , wherein the FEC module is a concatenated FEC module, and wherein the second-level functional unit further comprises an FEC encoding module configured to perform concatenated code encoding on data entering the second-level functional unit.
11 . The interface according to claim 1 , wherein the functional part 1 comprises a MAC module, a reconciliation sublayer (RS) module, an encode and rate matching module at a physical coding sublayer (PCS), and a transcode module.
12 . The interface according to claim 11 , wherein the functional part 2 comprises one or more functional units, the one or more functional units comprise a third functional unit, and wherein the third functional unit comprises a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, and a physical medium attachment sublayer (PMA)/physical medium dependent (PMD) module.
13 . The interface according to claim 11 , wherein the functional part 2 comprises one or more functional units, wherein the one or more functional units comprise a fourth functional unit, and the fourth functional unit comprises a module, an alignment marker insertion module, a forward error correction (FEC) module, and a physical medium attachment sublayer (PMA) module/a physical medium dependent (PMD) module.
14 . The interface according to claim 1 , wherein the functional part 1 comprises a MAC module, a reconciliation sublayer (RS) module, an encode and rate matching module at a physical coding sublayer (PCS), a transcode module, and a scramble module.
15 . The interface according to claim 14 , wherein the functional part 2 comprises one or more functional units, wherein the one or more functional units comprise a fifth functional unit, and the fifth functional unit comprises an alignment marker insertion module, a forward error correction (FEC) module, and a physical medium attachment sublayer (PMA)/physical medium dependent (PMD) module.
16 . The interface according to claim 1 , wherein the interface is an Ethernet interface with a rate of 800 Gb/s or 1.6 Tb/s.
17 . The interface according to claim 1 , wherein the transcode is an IEEE 802.3-2018-compliant 64B/66B-to-256B/257B transcode.
18 . The interface according to claim 1 , wherein a quantity of functional units comprised in the functional part 2 is 1, 2, 3, 4, 5, 8, or 16.
19 . The interface according to claim 1 , wherein the functional part 2 is coupled to the functional part 1 through a data block distribution module.
20 . The interface according to claim 1 , wherein the functional part 1 comprises a media independent interface.
21 . An electronic device, comprising:
an interface, where the interface comprises a functional part 1 and a functional part 2; wherein the functional part 1 is configured to implement processing dependent on a medium access control (MAC) rate; and wherein the functional part 2 is configured to implement processing independent of the MAC rate.
22 . A communication system, comprising:
a transmitter-side device; and a receiver-side device; wherein the transmitter-side device comprises an interface, where the interface comprises a functional part 1 and a functional part 2; wherein the functional part 1 is configured to implement processing dependent on a medium access control (MAC) rate; and wherein the functional part 2 is configured to implement processing independent of the MAC rate.Join the waitlist — get patent alerts
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