Device for testing chip or die with better system ir drop

Abstract

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

What is claimed is: 
     
         1 . A device for testing a chip or a die, comprising:
 a testing board having a plurality of pads, for providing a plurality of test signals; and   an interposer board, wherein the interposer board comprises a plurality of passive components, one electrode of at least one of the passive components is connected to a supply voltage, another electrode of the at least one of the passive components is connected to a ground voltage, and the interposer board receives the supply voltage and the ground voltage from a power pad and a ground pad of the plurality of pads of the testing board, respectively;   wherein the chip or the die is positioned in the device, the chip or the die is between the testing board and the interposer board, and the chip or the die receives the test signals comprising the supply voltage and the ground voltage from the testing board.   
     
     
         2 . The device of  claim 1 , further comprising:
 a connector, coupled between the testing board and the chip or the die, wherein the connector receives the test signals from the testing board and inputs the test signals into the chip or the die that is to be test;   wherein the interposer board receives the supply voltage and the ground voltage from the testing board via the connector and the chip.   
     
     
         3 . The device of  claim 1 , further comprising:
 a connector, coupled between the interposer board and the chip or the die, wherein the connector receives the supply voltage and the ground voltage from the testing board via the chip or the die;   wherein the interposer board receives the supply voltage and the ground voltage from the connector.   
     
     
         4 . The device of  claim 1 , wherein another chip is positioned in the device, the chip or the die is under the interposer board, the another chip is above the interposer board, and the another chip receives the test signals comprising the supply voltage and the ground voltage from the interposer board. 
     
     
         5 . The device of  claim 4 , wherein the another chip receives the test signals comprising the supply voltage and the ground voltage from the testing board via the chip or the die and the interposer board. 
     
     
         6 . The device of  claim 4 , wherein the interposer board has a first surface comprising a plurality of first pads and a second surface comprising a plurality of second pads, wherein the plurality of first pads are used to couple the chip or the die, and the plurality of second pads are used to connect to the another chip. 
     
     
         7 . The device of  claim 1 , wherein the plurality of passive components comprise a two-pin passive component. 
     
     
         8 . The device of  claim 7 , wherein the plurality of passive components comprise at least one capacitor. 
     
     
         9 . The device of  claim 7 , wherein the plurality of passive components comprise at least one inductor. 
     
     
         10 . The device of  claim 7 , wherein the plurality of passive components comprise at least one resistor. 
     
     
         11 . A device for testing a chip or a die, comprising:
 a testing board having a plurality of pads, for providing a plurality of test signals; and   an interposer board, wherein the interposer board comprises a plurality of passive components having a first passive component and a second passive component, one electrode of the first passive component is connected to a first supply voltage, another electrode of the first passive components is connected to a first ground voltage, one electrode of the second passive component is connected to a second supply voltage different from the first supply voltage, another electrode of the second passive components is connected to a second ground voltage different from the second supply voltage; and the interposer board receives the first supply voltage, the first ground voltage, the second supply voltage and the second ground voltage from the plurality of pads of the testing board;   wherein the chip or the die is positioned in the device, and the chip or the die receives the test signals comprising the supply voltage and the ground voltage from the testing board.   
     
     
         12 . The device of  claim 11 , further comprising:
 a first connector, for receiving the test signals from the interposer board, and inputting the test signals into the chip that is to be tested.   
     
     
         13 . The device of  claim 12 , wherein the interposer board is positioned between the testing board and the first connector, and the first connector receives the test signals via the interposer board. 
     
     
         14 . The device of  claim 11 , wherein the chip or the die is between the testing board and the interposer board. 
     
     
         15 . The device of  claim 14 , further comprising:
 a connector, coupled between the testing board and the chip or the die, wherein the connector receives the test signals from the testing board and inputs the test signals into the chip or the die that is to be test;   wherein the interposer board receives the supply voltage and the ground voltage from the testing board via the connector and the chip.   
     
     
         16 . The device of  claim 14 , further comprising:
 a connector, coupled between the interposer board and the chip or the die, wherein the connector receives the supply voltage and the ground voltage from the testing board via the chip or the die;   wherein the interposer board receives the supply voltage and the ground voltage from the connector.   
     
     
         17 . The device of  claim 14 , wherein another chip is positioned in the device, the chip or the die is under the interposer board, the another chip is above the interposer board, and the another chip receives the test signals comprising the supply voltage and the ground voltage from the interposer board. 
     
     
         18 . The device of  claim 11 , wherein the plurality of passive components comprise a two-pin passive component. 
     
     
         19 . The device of  claim 18 , wherein the plurality of passive components comprise at least one capacitor.