Finfet having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins

Abstract

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

What is claimed is: 
     
         1 . A structure, comprising:
 a plurality of semiconductor fins;   a liner structure disposed on the plurality of semiconductor fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the plurality of semiconductor fins, and the cap portion is covering a top surface of the plurality of semiconductor fins and joined with the sidewall portions;   a dielectric layer conformally covering the liner structure and across the plurality of semiconductor fins; and   a gate dielectric layer disposed on the dielectric layer and a gate electrode layer disposed on the gate dielectric layer.   
     
     
         2 . The structure according to  claim 1 , wherein a maximum thickness T 1  of the cap portion is greater than a thickness T 2  of the sidewall portions. 
     
     
         3 . The structure according to  claim 1 , further comprising spacer structures located on two sides of the gate dielectric layer, wherein side surfaces of the spacer structures are aligned with side surfaces of the dielectric layer. 
     
     
         4 . The structure according to  claim 3 , further comprising an interlayer dielectric layer covering the side surfaces of the spacer structures and the side surfaces of the dielectric layer. 
     
     
         5 . The structure according to  claim 4 , wherein a top surface of the interlayer dielectric layer is aligned with a top surface of the gate dielectric layer and a top surface of the gate electrode layer. 
     
     
         6 . The structure according to  claim 1 , further comprising a capping layer disposed in between the plurality of semiconductor fins and the liner structure, wherein the capping layer is in direct contact with the plurality of semiconductor fins. 
     
     
         7 . The structure according to  claim 1 , wherein a thickness of the dielectric layer is maintained to be the same along the sidewall portions and the cap portion of the liner structure. 
     
     
         8 . A structure, comprising:
 a substrate comprising at least one fin, wherein the fin comprises a first region and a second region;   a liner structure disposed on the first region of the fin;   a dielectric layer disposed on the first region of the fin over the liner structure;   a gate stack disposed on the first region of the fin over the dielectric layer;   strained material portions disposed on the second region of the fin; and   an interlayer dielectric layer disposed over the substrate and covering the strained material portions, wherein the interlayer dielectric layer is contacting side surfaces of the liner structure and side surfaces of the dielectric layer.   
     
     
         9 . The structure according to  claim 8 , further comprising a capping layer disposed on the first region and the second region of the fin, wherein the liner structure is located in between the capping layer and the gate stack in the first region, and the strained material portions are covering the capping layer in the second region. 
     
     
         10 . The structure according to  claim 9 , further comprising insulators disposed on the substrate and located below the liner structure, wherein the insulators are in direct contact with the capping layer and the liner structure. 
     
     
         11 . The structure according to  claim 8 , wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions are covering sidewalls of the fin, and the cap portion is covering a top surface of the fin and joined with the sidewall portions, and a maximum thickness T 1  of the cap portion is greater than a thickness T 2  of the sidewall portions. 
     
     
         12 . The structure according to  claim 11 , wherein the liner structure further includes base portions disposed over the substrate and joined with the sidewall portions, wherein a thickness T 3  of the base portions is substantially equal to the thickness T 2  of the sidewall portions. 
     
     
         13 . The structure according to  claim 8 , further comprising spacer structure disposed on two sides of the gate stack, wherein the interlayer dielectric layer is covering side surfaces of the spacer structure. 
     
     
         14 . The structure according to  claim 13 , wherein the side surfaces of the spacer structure are aligned with the side surfaces of the liner structure and the side surfaces of the dielectric layer. 
     
     
         15 . A structure, comprising:
 a substrate comprising semiconductor fins, wherein the semiconductor fins include a top surface and side surfaces joined with the top surface;   a liner structure, a first dielectric layer, a second dielectric layer and a gate electrode sequentially disposed on the semiconductor fins covering the top surface and the side surfaces of the semiconductor fins, wherein a thickness of the liner structure on the top surface of the semiconductor fins is greater than a thickness of the first dielectric layer and a thickness of the second dielectric layer on the top surface of the semiconductor fins.   
     
     
         16 . The structure according to  claim 15 , wherein a thickness of the liner structure on the side surfaces of the semiconductor fins is smaller than the thickness of the liner structure on the top surface of the semiconductor fins. 
     
     
         17 . The structure according to  claim 15 , wherein a thickness of the first dielectric layer on the side surfaces of the semiconductor fins is equal to the thickness of the first dielectric layer on the top surface of the semiconductor fins. 
     
     
         18 . The structure according to  claim 15 , further comprising a capping layer covering the semiconductor fins and located underneath the liner structure. 
     
     
         19 . The structure according to  claim 18 , wherein a bottom surface of the capping layer is aligned with a bottom surface of the liner structure. 
     
     
         20 . The structure according to  claim 18 , further comprising insulators disposed on the substrate and located underneath the capping layer and the liner structure.