Method and structure of single crystal electronic devices with enhanced strain interface regions by impurity introduction

Abstract

A method of manufacture and resulting structure for a single crystal electronic device with an enhanced strain interface region. The method of manufacture can include forming a nucleation layer overlying a substrate and forming a first and second single crystal layer overlying the nucleation layer. These first and second layers can be doped by introducing one or more impurity species to form the strained single crystal layers. The first and second strained layers can be aligned along the same crystallographic direction to form a strained single crystal bi-layer having an enhanced strain interface region. Using this enhanced single crystal bi-layer to form active or passive devices results in improved physical characteristics, such as enhanced photon velocity or improved density charges.

What is claimed is: 
     
         1 . A single crystal electronic device, the device comprising:
 a substrate having a substrate surface region;   a nucleation layer formed overlying the substrate surface region and being characterized by nucleation growth parameters; and   a first strained single crystal piezoelectric layer formed overlying the nucleation layer, the first strained single crystal piezoelectric layer including one or more impurity species including scandium (Sc) and being characterized by a first strain condition and first piezoelectric layer parameters;   a second strained single crystal piezoelectric layer formed overlying the first single crystal piezoelectric layer, the second strained single crystal piezoelectric layer including one or more impurity species including scandium (Sc) and being characterized by a second strain condition and second piezoelectric layer parameters; and   an interface region configured between the first strained single crystal piezoelectric layer and the second strained single crystal piezo electric layer.   
     
     
         2 . The device of  claim 1  wherein the substrate is selected from one of the following: a silicon substrate, a sapphire substrate, silicon carbide substrate, a GaN bulk substrate, a GaN template, an AlN bulk, an AlN template, Al x Ga 1-x N templates, engineered substrates such as silicon on insulator (SOI), and polycrystalline AlN templates. 
     
     
         3 . The device of  claim 1  wherein the nucleation layer and the first and second strained single crystal piezoelectric layers can include materials or alloys having at least one of the following: AlN, AlGaN, GaN, InN, InGaN, AlInN, AlInGaN, ScAlN, ScGaN, and BN. 
     
     
         4 . The device of  claim 1  wherein the nucleation growth parameters include temperature, pressure, thickness, growth rate, and gas phase ratio of reactant species; and wherein the first and second piezoelectric layer parameters include acoustic velocity, nucleation layer formation and transition conditions, growth temperature, growth pressure, layer thickness, growth rate, and gas phase ratio. 
     
     
         5 . The device of  claim 1  wherein the one or more impurity species has an impurity concentration ranging from about 1E+10 to about 1E+21 per cubic centimeter. 
     
     
         6 . The device of  claim 1  wherein the first or second strained single crystal piezoelectric material has a thickness greater than 0.4 microns and is characterized by a dislocation density less than 10 12  defects/cm 2 . 
     
     
         7 . The device of  claim 1  wherein the first and second strained single crystal piezoelectric layers are configured such that the first and second strain conditions are aligned in the same crystallographic direction at the interface region. 
     
     
         8 . A single crystal electronic device, the device comprising:
 a substrate having a substrate surface region;   a nucleation layer formed overlying the substrate surface region and being characterized by nucleation growth parameters; and   an enhanced single crystal bi-layer formed overlying the nucleation layer, wherein the enhanced single crystal bi-layer includes
 a first strained single crystal piezoelectric layer formed overlying the nucleation layer, the first strained single crystal piezoelectric layer being characterized by a first strain condition and first piezoelectric layer parameters; 
 a second strained single crystal piezoelectric layer formed overlying the first single crystal piezoelectric layer, the second strained single crystal piezoelectric layer including one or more impurity species being characterized by a second strain condition and second piezoelectric layer parameters; and 
 an interface region configured between the first strained single crystal piezoelectric layer and the second strained single crystal piezo electric layer. 
   
     
     
         9 . The device of  claim 8  wherein the first and second strained single crystal piezoelectric layers are configured such that the first and second strain conditions are aligned in the same crystallographic direction at the interface region. 
     
     
         10 . The device of  claim 8  wherein the first and second strained single crystal piezoelectric layers include one or more impurity species characterizing the first and second strain conditions. 
     
     
         11 . The device of  claim 10  wherein the one or more impurity species include silicon (Si), magnesium (Mg), carbon (C), oxygen (O), erbium (Er), rubidium (Rb), strontium (Sr), scandium (Sc), beryllium (Be), molybdenum (Mo), zirconium (Zr), Hafnium (Hf), or vanadium (Va).