A scalable polylithic on-package integratable apparatus and method

Abstract

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

1 . An apparatus having a plurality of heterogeneous dies, including logic dies and an input-output (IO) die, the plurality of heterogeneous dies integratable together in a single polylithic package to provide configurable number of logic dies and IO dies in manufacture, the apparatus formed by a process comprising:
 determining a desired configuration of the apparatus;   arranging a number of logic dies according to the desired configuration, wherein each of the logic dies include a plurality of cores, switching circuitry coupled to the plurality of cores, and a communication interface coupled to the switching circuitry;   arranging a second die according to the desired configuration, the second die comprising:
 an edge interface positioned at a periphery of the second die; 
 a clock synchronization circuit coupled to the edge interface of the second die; and 
 a memory interface coupled to the clock synchronization circuit, wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the edge interface of the second die; and 
   coupling the number of logic dies and the second die, wherein the edge interface of the second die is coupled to the communication interface of at least one of the logic dies via a corresponding package-level interconnect and wherein the second die is the IO die.   
     
     
         2 . The apparatus of  claim 1 , wherein the logic dies are processor dies, accelerator dies or a combination thereof. 
     
     
         3 . The apparatus of  claim 2 , wherein the number of processor dies is 2. 
     
     
         4 . The apparatus of  claim 2 , wherein the number of processor dies is 4. 
     
     
         5 . The apparatus of  claim 2 , wherein the number of processor dies is 8. 
     
     
         6 . The apparatus of  claim 1 , wherein the number of logic dies are manufactured on a first process technology node and the second die is manufactured on a second process technology node different from the first process technology node. 
     
     
         7 . The apparatus of  claim 1 , wherein the second die and the at least one of the logic dies are coupled via a hierarchical fabric. 
     
     
         8 . The apparatus of  claim 1 , wherein the second die is a memory or network IO chip fabricated on a silicon substrate. 
     
     
         9 . The apparatus of  claim 1 , wherein the logic dies and the second die are on a single package. 
     
     
         10 . A method comprising:
 arranging a plurality of first dies each having edge interfaces and crossbar switches;   arranging a plurality of second dies each having edge interfaces and crossbar switches;   coupling one or more edge interfaces of at least two of the first dies with one or more edge interfaces of at least two of the second dies;   coupling a third die with at least one of the first dies, the third die having an edge interface coupled to an edge interface of the at least one of the first die, and having a memory interface, wherein the third die includes:
 a clock synchronization circuit coupled to the edge interface of the second die, wherein the memory interface is coupled to the clock synchronization circuit, and wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the edge interface of the second die; and 
   coupling a fourth die with at least one of the second dies, the fourth die having an edge interface coupled to an edge interface of the at least one of the second dies, and having a network interface.   
     
     
         11 . The method of  claim 10 , wherein coupling the one or more edge interfaces of the at least two of the first dies with the one or more edge interfaces of the at least two of the second dies comprises:
 establishing at least two embedded bridges between the at least two edge interfaces of the at least two of the first dies and the at least two edge interfaces of the at least two of the second dies.   
     
     
         12 . The method of  claim 10  comprises packaging the first, second, third, and fourth dies in a single package. 
     
     
         13 . The method of  claim 10  comprises establishing embedded bridges to couple the edge interfaces of the first, second, third, and fourth dies. 
     
     
         14 . A method comprising:
 determining a desired configuration of a chip;   arranging a number of the first dies according to the desired configuration, wherein each of the first dies includes a processor core and a standardized interface, wherein the number of first dies includes die of a first type and die of a second type, wherein the die of the first type directly interconnects with the die of the second type via the standardized interface; and   coupling at least one of the die of the first type or the die of the second type with a second die, wherein the second die is an IO die,   wherein at least one of the die of the first type or the die of the second type includes a clock synchronization circuit coupled to the standardized interface,   wherein a memory interface is coupled to the clock synchronization circuit, and   wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the standardized interface.   
     
     
         15 . The method of  claim 14 , wherein the number of first dies is 2. 
     
     
         16 . The method of  claim 14 , wherein the number of processor dies is 4. 
     
     
         17 . The method of  claim 14 , wherein the number of first dies is 8. 
     
     
         18 . The method of  claim 14 , wherein the die of the first type and the die of the second type are of different process technology nodes. 
     
     
         19 . The method of  claim 14 , wherein the die of the first type and the die of the second type are coupled via a hierarchical fabric.