Vertical non-volatile memory device

Abstract

A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

What is claimed is: 
     
         1 . A vertical non-volatile memory device comprising:
 a substrate;   a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate;   a plurality of insulating layers between the gate lines;   a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate; and   a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.   
     
     
         2 . The vertical non-volatile memory device of  claim 1 , wherein the contact electrode is electrically separated from the plurality of gate lines other than the uppermost gate line by the separation insulating layers in the horizontal direction. 
     
     
         3 . The vertical non-volatile memory device of  claim 1 , further comprising:
 a plurality of filling insulating layers between the separation insulating layers and the insulating layers in the horizontal direction inside the contact hole.   
     
     
         4 . The vertical non-volatile memory device of  claim 1 , wherein the substrate defines a portion of a bottom of the contact hole. 
     
     
         5 . The vertical non-volatile memory device of  claim 1 , further comprising:
 a buried insulating layer in the contact hole,   wherein the contact electrode is on the buried insulating layer.   
     
     
         6 . The vertical non-volatile memory device of  claim 1 , further comprising:
 an etching blocking insulating layer on one side of the separation insulating layers and a portion of a bottom of the contact hole.   
     
     
         7 . The vertical non-volatile memory device of  claim 1 , wherein the contact electrode is below an upper surface of the contact gate stack structure in the contact hole. 
     
     
         8 . The vertical non-volatile memory device of  claim 1 , wherein the contact gate stack structure comprises:
 a lower contact gate stack structure, an intermediate contact gate stack structure, and an upper contact gate stack structure sequentially stacked on the substrate; and   a first intermediate insulating layer and a second intermediate insulating layer between the lower contact gate stack structure and the intermediate contact gate stack structure, and between the intermediate contact gate stack structure and the upper contact gate stack structure, respectively,   wherein the first intermediate insulating layer and the second intermediate insulating layer are thicker than the insulating layers.   
     
     
         9 . The vertical non-volatile memory device of  claim 1 , further comprising:
 a plurality of composite films between the substrate and the plurality of gate lines on the substrate.   
     
     
         10 . A vertical non-volatile memory device comprising:
 a memory cell area including memory cells on a substrate; and   a connection area at one side of the memory cell area in a horizontal direction and electrically connected to the memory cell area, the horizontal direction being horizontal to a surface of the substrate,   wherein the connection area includes,
 a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate and a plurality of insulating layers between the gate lines, the vertical direction being perpendicular to the surface of the substrate, 
 a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in the horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole; 
 a buried insulating layer buried in the contact hole; and 
 a contact electrode on the buried insulating layer and the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines. 
   
     
     
         11 . The vertical non-volatile memory device of  claim 10 , wherein
 the contact gate stack structure includes a plurality of contact gate stack structures in a step area in the horizontal direction from the memory cell area, and   the plurality of contact gate stack structures includes the separation insulating layers and the contact electrode.   
     
     
         12 . The vertical non-volatile memory device of  claim 10 , wherein the contact gate stack structure comprises:
 a lower contact gate stack structure on the substrate; and   a cover insulating layer on the lower contact gate stack structure.   
     
     
         13 . The vertical non-volatile memory device of  claim 10 , wherein
 the buried insulating layer is partially buried in the contact hole, and   the contact electrode is on the buried insulating layer buried partially.   
     
     
         14 . The vertical non-volatile memory device of  claim 10 , further comprising:
 a plurality of filling insulating layers between the separation insulating layers and the insulating layers in the horizontal direction inside the contact hole; and   an etching blocking insulating layer in contact with the buried insulating layer on one side of the separation insulating layers and the filling insulating layers, and on a bottom part of the contact hole.   
     
     
         15 . A vertical non-volatile memory device comprising:
 a memory cell area including memory cells on a first substrate;   a through electrode area at one side of the memory cell area in a horizontal direction and electrically connected to a peripheral circuit wiring layer of a second substrate below the first substrate, the horizontal direction being horizontal to a surface of the first substrate; and   a contact area at one side of a through electrode in the horizontal direction and electrically connected to the memory cell area,   wherein the through electrode area includes,
 an insulator stack structure including
 a through insulating layer penetrating the first substrate, 
 a plurality of sacrificial films stacked in the vertical direction on the through insulating layer, and 
 a plurality of first insulating layers between the sacrificial films, and a through hole extending in the vertical direction from the peripheral circuit wiring layer of the second substrate inside the insulator stack structure and exposing the peripheral circuit wiring layer and a through electrode buried in the through hole, wherein the contact area includes, 
 
 a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the first substrate and a plurality of second insulating layers between the gate lines, the vertical direction being perpendicular to the surface of the first substrate, 
 a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in the horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, 
 a buried insulating layer buried in the contact hole, and 
 a contact electrode on the buried insulating layer and the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines. 
   
     
     
         16 . The vertical non-volatile memory device of  claim 15 , wherein the sacrificial films of the through electrode area are at a same level as the plurality of gate lines of the contact area. 
     
     
         17 . The vertical non-volatile memory device of  claim 15 , wherein the first insulating layers of the through electrode area are at a same level as the second insulating layers of the contact area. 
     
     
         18 . The vertical non-volatile memory device of  claim 15 , further comprising:
 a plurality of first filling insulating layers between protruding portions of the sacrificial lines in the through hole, the protruding portions of the sacrificial films protruding from an inner wall of the through hole.   
     
     
         19 . The vertical non-volatile memory device of  claim 15 , wherein the contact area comprises:
 a plurality of contact gate stack structures in a step area in the horizontal direction from the memory cell area,   wherein the plurality of contact gate structures includes the separation insulating layers and the contact electrode.   
     
     
         20 . The vertical non-volatile memory device of  claim 15 , further comprising:
 a plurality of second filling insulating layers between the separation insulating layers and the second insulating layers in the horizontal direction inside the contact hole, and   an etching blocking insulating layer in contact with the buried insulating layer on one side of the separation insulating layers and the second filling insulating layers, and on a bottom portion of the contact hole.