Adjustable programming circuit for neural network

Abstract

Examples of programming circuits and methods are disclosed. In one example, an adjustable programming circuit for generating a programming voltage is disclosed, the circuit comprising an operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving a reference voltage; a first switched capacitor network coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and a second switched capacitor network coupled between an input voltage and the second input terminal of the operational amplifier; wherein the output terminal of the operational amplifier outputs a programming voltage that varies in response to a capacitance of the first switched capacitor network and a capacitance of the second switched capacitor network.

What is claimed is: 
     
         1 . An adjustable programming circuit for generating a programming voltage that comprises one of a plurality of different voltages to program a non-volatile memory cell for a neural network to store one of a plurality of different voltages on a floating gate of the non-volatile memory cell, comprising:
 an operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving a reference voltage;   a first switched capacitor network coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and   a second switched capacitor network coupled between an input voltage and the second input terminal of the operational amplifier;   wherein the output terminal of the operational amplifier outputs a programming voltage that varies in response to a capacitance of the first switched capacitor network and a capacitance of the second switched capacitor network.   
     
     
         2 . The adjustable programming circuit of  claim 1 , wherein the first switched capacitor network comprises an adjustable capacitor. 
     
     
         3 . The adjustable programming circuit of  claim 1 , wherein the second switched capacitor network comprises an adjustable capacitor. 
     
     
         4 . The adjustable programming circuit of  claim 2 , wherein the second switched capacitor network comprises an adjustable capacitor. 
     
     
         5 . The adjustable programming circuit of  claim 1 , wherein the non-volatile memory cell is a stacked-gate memory cell. 
     
     
         6 . The adjustable programming circuit of  claim 1 , wherein the non-volatile memory cell is a split-gate memory cell. 
     
     
         7 . A method of generating a programming voltage by an adjustable programming circuit comprising an operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, a first switched capacitor network coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier, and a second switched capacitor network coupled between an input voltage and the second input terminal of the operational amplifier, the method comprising:
 receiving, by the first input terminal of the operational amplifier, a reference voltage;   outputting, by the output terminal of the operational amplifier, a programming voltage that varies in response to a capacitance of the first switched capacitor network and a capacitance of the second switched capacitor network; and   applying the programming voltage to a non-volatile memory cell for a neural network to store one of a plurality of different voltages on a floating gate of the non-volatile memory cell.   
     
     
         8 . The method of  claim 7 , wherein the first switched capacitor network comprises an adjustable capacitor. 
     
     
         9 . The method of  claim 7 , wherein the second switched capacitor network comprises an adjustable capacitor. 
     
     
         10 . The method of  claim 9 , wherein the second switched capacitor network comprises an adjustable capacitor. 
     
     
         11 . The method of  claim 7 , wherein the non-volatile memory cell is a stacked-gate memory cell. 
     
     
         12 . The method of  claim 7 , wherein the non-volatile memory cell is a split-gate memory cell.