Semiconductor device and electronic device

Abstract

To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first transistor, the first transistor comprising:
 an oxide semiconductor layer; 
 a first insulator comprising a first opening; 
 a first electrode isolated from the oxide semiconductor layer; 
 a second electrode in the first opening, 
   a second transistor; and   a capacitor comprising:
 the first insulator; and 
 a third electrode in contact with a top of the first insulator, 
   wherein the oxide semiconductor layer comprises a source region, a drain region, and a first channel formation region,   wherein the first insulator is provided between the oxide semiconductor layer and the first electrode,   wherein in a plane perpendicular to a channel length direction, the first channel formation region is surrounded along all sides by the first electrode,   wherein in a plan view, a bottom surface of the first electrode protrudes from a top surface of the first electrode,   wherein the source region is configured to be one of an electrode of the capacitor,   wherein the drain region comprises the first opening,   wherein the third electrode is configured to be the other of an electrode of the capacitor, and   wherein the second electrode is electrically connected with the second transistor.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein a length of the first channel formation region is less than or equal to 20 nm,   wherein a width of the first channel formation region is less than or equal to 20 nm, and   wherein a thickness of the first channel formation region is greater than or equal to 10 nm.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein each of the source region and the drain region has lower resistance than the first channel formation region.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein an impurity concentration is higher in each of the source region and the drain region than in the first channel formation region.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein, in a plan view, the first electrode and the third electrode do not overlap,   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the second transistor comprising silicon in a second channel formation region.   
     
     
         7 . An electronic device comprising the semiconductor device according to  claim 1 . 
     
     
         8 . A semiconductor device comprising:
 a first transistor, the first transistor comprising:
 an oxide semiconductor layer; 
 a first insulator comprising a first opening; 
 a first electrode isolated from the oxide semiconductor layer; 
 a second electrode in the first opening, 
   a second transistor; and   a capacitor comprising:
 the first insulator; and 
 a third electrode in contact with a top of the first insulator, 
   wherein the oxide semiconductor layer comprises a source region, a drain region, and a first channel formation region,   wherein in a plane perpendicular to a channel length direction, the first channel formation region is surrounded along all sides by the first electrode,   wherein the first electrode comprises a first conductive layer below the oxide semiconductor layer and a second conductive layer over the oxide semiconductor layer,   wherein, in a plan view, the first conductive layer protrudes from the second conductive layer in all directions,   wherein the source region is configured to be one of an electrode of the capacitor,   wherein the drain region comprises the first opening,   wherein the third electrode is configured to be the other of an electrode of the capacitor, and   wherein the second electrode is electrically connected with the second transistor.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein a length of the first channel formation region is less than or equal to 20 nm,   wherein a width of the first channel formation region is less than or equal to 20 nm, and   wherein a thickness of the first channel formation region is greater than or equal to 10 nm.   
     
     
         10 . The semiconductor device according to  claim 8 ,
 wherein each of the source region and the drain region has lower resistance than the first channel formation region.   
     
     
         11 . The semiconductor device according to  claim 8 ,
 wherein an impurity concentration is higher in each of the source region and the drain region than in the first channel formation region.   
     
     
         12 . The semiconductor device according to  claim 8 ,
 wherein, in a plan view, the first electrode and the third electrode do not overlap,   
     
     
         13 . The semiconductor device according to  claim 8 ,
 wherein the second transistor comprising silicon in a second channel formation region.   
     
     
         14 . An electronic device comprising the semiconductor device according to  claim 8 . 
     
     
         15 . A semiconductor device comprising:
 a first transistor, the first transistor comprising:
 a first conductor; 
 a first insulator comprising a first opening; 
 an oxide semiconductor layer over the first insulator; 
 a second insulator comprising the first opening; 
 a second conductor over the second insulator; 
 a third conductor in the first opening, 
   a second transistor; and   a capacitor comprising:
 the second insulator; and 
 a fourth conductor in contact with a top of the second insulator, 
   wherein the oxide semiconductor layer comprises a first region and a second region,   wherein an interface between the first region and the second region is aligned with an edge of the second conductor,   wherein, in a plane parallel to the interface between the first region and the second region, the oxide semiconductor layer is surrounded along all sides by the first conductor and the second conductor with the first insulator and the second insulator interposed therebetween,   wherein, in a plan view, the first conductor protrudes from the second conductor,   wherein the third conductor is in direct contact with the first region through the first opening,   wherein the first region is configured to be one of an electrode of the capacitor,   wherein the first region comprises the first opening,   wherein the fourth conductor is configured to be the other of an electrode of the capacitor, and   wherein the third conductor is electrically connected with the second transistor.   
     
     
         16 . The semiconductor device according to  claim 15 ,
 wherein a length of the second region is less than or equal to 20 nm,   wherein a width of the second region is less than or equal to 20 nm, and   wherein a thickness of the second region is greater than or equal to 10 nm.   
     
     
         17 . The semiconductor device according to  claim 15 ,
 wherein the first region has lower resistance than the second region.   
     
     
         18 . The semiconductor device according to  claim 15 ,
 wherein an impurity concentration is higher in the first region than in the second region.   
     
     
         19 . The semiconductor device according to  claim 15 ,
 wherein, in a plan view, the first conductor and the third conductor do not overlap,   wherein, in a plan view, the second conductor and the third conductor do not overlap,   
     
     
         20 . The semiconductor device according to  claim 15 ,
 wherein the second transistor comprising silicon in a channel formation region.   
     
     
         21 . An electronic device comprising the semiconductor device according to  claim 15 .