Less-secure processors, integrated circuits, wireless communications apparatus, methods for operation thereof, and methods for manufacturing thereof

Abstract

An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

What is claimed is: 
     
         1 . A system comprising:
 a memory configured to store a first boot code portion, a second boot code portion, and a third boot code portion, wherein:
 the first boot code portion and the second boot code portion are associated with a first security mode; and 
 the third boot code portion is associated with a second security mode that is less secure than the first security mode; 
   a storage element configured to store a value that is associated with either the first security mode or the second security mode; and   a processor coupled to the memory and to the storage element and configured to:   execute the first boot code portion to select whether to execute the second boot code portion or the third boot code portion based on the value.   
     
     
         2 . The system of  claim 1 , wherein the processor is configured to:
 execute the first boot code portion in the first security mode; and   based on the value being associated with the second security mode:
 convert from the first security mode to the second security mode; and 
 execute the third boot code portion in the second security mode. 
   
     
     
         3 . The system of  claim 1  further comprising security circuitry coupled to the processor, wherein the processor is configured to:
 execute the second boot code portion to cause the security circuitry to operate in the first security mode; and 
 execute the third boot code portion to cause the security circuitry to operate in the second security mode. 
 
     
     
         4 . The system of  claim 3 , wherein an access of the security circuitry is prevented in the first security mode and permitted in the second security mode. 
     
     
         5 . The system of  claim 3 , wherein the security circuitry includes a secure hardware accelerator. 
     
     
         6 . The system of  claim 5 , wherein the secure hardware accelerator is configured to perform at least one of encryption or decryption. 
     
     
         7 . The system of  claim 5 , wherein the secure hardware accelerator is configured perform encryption based on at least one of a hashing algorithm, a symmetric encryption algorithm, or an asymmetric encryption algorithm. 
     
     
         8 . The system of  claim 3 , wherein the security circuitry includes a secure watchdog timer. 
     
     
         9 . The system of  claim 8 , wherein the secure watchdog timer is enabled in the first security mode and disabled in the second security mode. 
     
     
         10 . The system of  claim 1  wherein the memory includes:
 a secure portion configured to store the first boot code portion and the second boot code portion; and 
 a public portion configured to store the third boot code portion. 
 
     
     
         11 . The system of  claim 1 , wherein the storage element includes non-volatile storage. 
     
     
         12 . The system of  claim 11 , wherein the non-volatile storage is one-time programmable. 
     
     
         13 . The system of  claim 11 , wherein the non-volatile storage includes electronic fuse (eFuse) circuitry. 
     
     
         14 . The system of  claim 11 , wherein the first and second security modes are represented by two bits in the storage element. 
     
     
         15 . The system of  claim 1 , wherein the memory is a read-only memory (ROM).