Methods, systems and apparatus to improve convolution efficiency

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to improve convolution efficiency of a convolution neural network (CNN) accelerator. An example hardware accelerator includes a hardware data path element (DPE) in a DPE array, the hardware DPE including an accumulator, and a multiplier coupled to the accumulator, the multiplier to multiply first inputs including an activation value and a filter coefficient value to generate a first convolution output when the hardware DPE is in a convolution mode, and a controller coupled to the DPE array, the controller to adjust the hardware DPE from the convolution mode to a pooling mode by causing at least one of the multiplier or the accumulator to generate a second convolution output based on second inputs, the second inputs including an output location value of a pool area, at least one of the first inputs different from at least one of the second inputs.

1 - 20 . (canceled) 
     
     
         21 . First data path element circuitry of a hardware accelerator comprising:
 an accumulator;   a multiplier coupled to the accumulator;   a data input interface;   an adjacent data interface coupled to second data path element circuitry, the second data path element circuitry different from the first data path element circuitry;   a first switch coupled to the data input interface and the adjacent data interface; and   a second switch coupled to the first switch, a first interface, and a first input of the multiplier.   
     
     
         22 . The first data path element circuitry of  claim 21 , wherein the adjacent data interface is coupled to the accumulator via at least one of first circuitry or second circuitry. 
     
     
         23 . The first data path element circuitry of  claim 21 , wherein the data input interface is to be coupled to an output of a multiplexer. 
     
     
         24 . The first data path element circuitry of  claim 21 , further including an enable interface coupled to a second input of the multiplier, the enable interface to be coupled to an output of a controller. 
     
     
         25 . The first data path element circuitry of  claim 21 , further including:
 a bypass selector interface coupled to the multiplier;   a third switch coupled to a first output of the multiplier and a second output of the multiplier; and   a bypass interface coupled to the third switch.   
     
     
         26 . The first data path element circuitry of  claim 21 , wherein an output of the multiplier is coupled to an input of the accumulator, and further including:
 a third switch coupled to the input of the accumulator and an output of the accumulator; and   a bypass interface coupled to the third switch.   
     
     
         27 . The first data path element circuitry of  claim 21 , further including:
 a third switch coupled to an output of the multiplier and an input of the accumulator; and   a fourth switch coupled to the third switch, the input of the accumulator, and an output of the accumulator.   
     
     
         28 . The first data path element circuitry of  claim 21 , further including:
 a third switch coupled to an output of the accumulator;   a fourth switch coupled to the third switch;   a data output interface coupled to the fourth switch; and   a register coupled to the third switch and the fourth switch.   
     
     
         29 . Data path element circuitry of a hardware accelerator comprising:
 an accumulator;   a multiplier coupled to the accumulator;   a first switch coupled to a first output of the multiplier and a second output of the multiplier;   a first bypass interface coupled to the first switch;   a second switch coupled to an input of the accumulator and an output of the accumulator; and   a second bypass interface coupled to the second switch.   
     
     
         30 . The data path element circuitry of  claim 29 , further including a bypass selector interface coupled to the multiplier, the multiplier to output a first data value to the first output in response to the bypass selector interface providing a first logic value to the multiplier, and the multiplier to output a second data value to the second output in response to the bypass selector interface providing a second logic value to the multiplier. 
     
     
         31 . The data path element circuitry of  claim 29 , further including:
 a third switch coupled to an input of the multiplier;   a parametric rectified linear unit interface coupled to the third switch;   a fourth switch coupled to the third switch and an average pooling interface; and   a fifth switch coupled to the third switch and a parametric rectified linear unit switch interface.   
     
     
         32 . The data path element circuitry of  claim 31 , wherein the fourth switch is configured to provide a bias value, a coefficient value, or a scale value from a coefficient data store to the multiplier. 
     
     
         33 . The data path element circuitry of  claim 31 , wherein the fifth switch is configured to provide a first parametric rectified linear unit parameter or a second parametric rectified linear unit parameter to the multiplier. 
     
     
         34 . The data path element circuitry of  claim 29 , further including:
 a data input interface;   an enable interface coupled to the multiplier;   a third switch coupled to a first input of the multiplier;   a fourth switch coupled to the third switch and the data input interface; and   an adjacent data input interface coupled to the fourth switch.   
     
     
         35 . Data path element circuitry of a hardware accelerator comprising:
 a multiplier;   an accumulator in circuit with an output of the multiplier;   a first switch in circuit with an output of the accumulator;   a register in circuit with the output of the accumulator through the first switch;   a second switch in circuit with the first switch, a first input of the register, and a second input of the register;   a third switch in circuit with an output of the register and an input of the multiplier;   a clear register interface in circuit with a third input of the register; and   a store interface in circuit with a fourth input of the register.   
     
     
         36 . The data path element circuitry of  claim 35 , wherein the second switch is in circuit with a data output interface, and the data output interface to be in circuit with an output buffer. 
     
     
         37 . The data path element circuitry of  claim 35 , further including a comparator with a first input and a second input, the first input in circuit with the output of the register and the third switch, and the second input in circuit with a fourth switch. 
     
     
         38 . The data path element circuitry of  claim 37 , further including a fifth switch in circuit with the third switch, the fourth switch, and the output of the accumulator. 
     
     
         39 . The data path element circuitry of  claim 37 , wherein the fourth switch is configured to provide a first value of a parametric rectified linear unit base parameter or a second value of a rectified linear unit parameter to the second input of the comparator. 
     
     
         40 . The data path element circuitry of  claim 37 , further including a flip-flop, and an output of the comparator in circuit with an input of the flip-flop.