Lightning protection spark gaps for cable devices

Abstract

A spark gap circuit includes a circuit board. The spark gap circuit also includes an input configured to connect to the circuit board and to receive signals. The spark gap circuit also includes a spark gap configured to connect to the circuit board and the input. The spark gap circuit also includes an output configured to connect to the spark gap. The spark gap is configured to cause a return loss between the input and the output to be within a first predetermined range. The spark gap is configured to cause a parasitic capacitance between the input and the output to be within a second predetermined range.

What is claimed is: 
     
         1 . A spark gap circuit configured to achieve an enhanced return loss or enhanced parasitic capacitance, comprising:
 a circuit board;   an input configured to connect to the circuit board and to receive signals;   a spark gap configured to connect to the circuit board and the input, the spark gap comprising:
 a first conducting electrode; and 
 a second conducting electrode; 
   a first capacitor configured to connect to the circuit board and the spark gap;   a second capacitor configured to connect to the circuit board and the first capacitor;   an output configured to connect to the circuit board and the second capacitor;   wherein the spark gap is configured to cause a return loss between the input and the output to be within a first predetermined range; and   wherein the spark gap is configured to cause a parasitic capacitance between the input and the output to be within a second predetermined range.   
     
     
         2 . The spark gap circuit of  claim 1 , wherein the first predetermined range of the return loss is between about 15 dB to about 40 dB. 
     
     
         3 . The spark gap circuit of  claim 1 , wherein the second predetermined range of the parasitic capacitance is from about 0.01 pF to about 0.1 pF. 
     
     
         4 . The spark gap circuit of  claim 1 , wherein the first capacitor and the second capacitor are configured to block direct current (DC) flow therethrough and to provide surge protection. 
     
     
         5 . The spark gap circuit of  claim 1 , wherein the first capacitor and the second capacitor are connected in series. 
     
     
         6 . The spark gap circuit of  claim 1 , wherein the first capacitor is configured to be connected to the circuit board and the spark gap. 
     
     
         7 . The spark gap circuit of  claim 1 , wherein the second capacitor is configured to be connected to the circuit board, the first capacitor, and the output. 
     
     
         8 . A spark gap circuit, configured to achieve an enhanced return loss comprising:
 a circuit board;   an input configured to connect to the circuit board and to receive signals;   a spark gap configured to connect to the circuit board and the input;   an output configured to connect to the spark gap;   a first conducting electrode;   a second conducting electrode that is grounded;   a first capacitor configured to connect to the circuit board and the spark gap;   a second capacitor configured to connect to the circuit board, the first capacitor, and the output; and   wherein the spark gap is configured to cause a return loss between the input and the output to be within a first predetermined range.   
     
     
         9 . The spark gap circuit of  claim 8 , wherein the first predetermined range of the return loss is between about 15 dB to about 40 dB. 
     
     
         10 . The spark gap circuit of  claim 8 , wherein the spark gap is configured to cause a parasitic capacitance between the input and the output to be within a second predetermined range. 
     
     
         11 . The spark gap circuit of  claim 10 , wherein the second predetermined range of the parasitic capacitance is from about 0.01 pF to about 0.1 pF. 
     
     
         12 . The spark gap circuit of  claim 8 , wherein the first capacitor and the second capacitor are connected together in series. 
     
     
         13 . The spark gap circuit of  claim 8 , wherein the first capacitor and the second capacitor are configured to block direct current (DC) flow therethrough and to provide surge protection. 
     
     
         14 . The spark gap circuit of  claim 8 , wherein the input is configured to receive signals. 
     
     
         15 . A spark gap circuit configured to achieve an enhanced return loss or enhanced parasitic capacitance comprising:
 a spark gap structure configured to be connected to a circuit board;   a capacitor structure configured to store an electrical charge;   wherein the spark gap structure is configured to generate an enhanced return loss or an enhanced parasitic capacitance of the spark gap circuit;   wherein the enhanced return loss comprises a predetermined return loss level;   wherein the predetermined return loss level is between about 15 dB to about 40 dB; and   wherein the enhanced parasitic capacitance comprises a predetermined parasitic capacitance level.   
     
     
         16 . The spark gap circuit of  claim 15 , wherein the predetermined parasitic capacitance level is from about 0.01 pF to about 0.1 pF. 
     
     
         17 . The spark gap circuit of  claim 15 , wherein the capacitor structure is configured to block direct current (DC) flow therethrough and to provide surge protection. 
     
     
         18 . The spark gap circuit of  claim 15 , wherein the capacitor structure comprises a first capacitor and a second capacitor connected in series. 
     
     
         19 . The spark gap circuit of  claim 18 , wherein the first capacitor is configured to be connected to the circuit board and the spark gap structure. 
     
     
         20 . The spark gap circuit of  claim 18 , wherein the second capacitor is configured to be connected to the circuit board, the first capacitor, and the output.