Processor with table lookup unit

Abstract

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

What is claimed is: 
     
         1 . A device comprising:
 a decoder configured to couple to a processor;   a memory interface coupled to the decoder and configured to couple to a memory;   a set of vector registers coupled to the memory interface;   a set of processing elements coupled to the set of vector registers in parallel; and   a table lookup unit coupled to the set of vector registers in parallel with the set of processing element, wherein the decoder is configured to:
 receive a vector command that specifies a first set of data in the memory using a set of loops; and 
 based on the vector command:
 cause the memory interface to copy the first set of data from the memory to the set of vector registers; and 
 cause either the set of processing elements or the table lookup unit to perform an operation on the first set of data to produce a second set of data. 
 
   
     
     
         2 . The device of  claim 1 , wherein the vector command specifies whether the set of processing elements or the table lookup unit is to perform the operation on the first set of data to produce the second set of data. 
     
     
         3 . The device of  claim 1 , wherein the set of processing elements are configured to perform at least one of: bit interleaving, bit deinterleaving, conditional movement, conditional swap, sort, addition, logical AND, or logical OR on the first set of data. 
     
     
         4 . The device of  claim 1 , wherein the table lookup unit is configured to retrieve a subset of the first set of data to produce the second set of data. 
     
     
         5 . The device of  claim 1  further comprising a histogram unit coupled to the set of vector registers in parallel with the set of processing element and the table lookup unit. 
     
     
         6 . The device of  claim 1 , wherein the decoder is configured to cause the second set of data to be stored in the set of vector registers. 
     
     
         7 . The device of  claim 1  further comprising a write buffer coupled to the set of processing elements and the table lookup unit and configured to couple to the memory, wherein the decoder is configured to cause the second set of data to be stored in either the set of vector registers or the write buffer. 
     
     
         8 . The device of  claim 7 , wherein the memory interface is configured to cause the second set of data stored in the write buffer to be stored in the memory. 
     
     
         9 . The device of  claim 1  further comprising the processor coupled to the decoder. 
     
     
         10 . A device comprising:
 a processor;   a vector coprocessor coupled to the processor that includes:
 a decoder coupled to the processor; 
 a set of vector registers coupled to the decoder; 
 a set of processing elements coupled to the set of vector registers in parallel; and 
 a table lookup unit coupled to the set of vector registers in parallel with the set of processing element, wherein the decoder is configured to:
 receive a command from the processor that specifies a first set of data in a memory using a set of loops; and 
 based on the command, cause either the set of processing elements or the table lookup unit to perform an operation on the first set of data to produce a second set of data. 
 
   
     
     
         11 . The device of  claim 10 , wherein the decoder is configured to cause the first set of data to be copied from the memory to the set of vector registers. 
     
     
         12 . The device of  claim 10 , wherein the command specifies whether the set of processing elements or the table lookup unit is to perform the operation on the first set of data to produce the second set of data. 
     
     
         13 . The device of  claim 10 , wherein the set of processing elements are configured to perform at least one of: bit interleaving, bit deinterleaving, conditional movement, conditional swap, sort, addition, logical AND, or logical OR on the first set of data. 
     
     
         14 . The device of  claim 10 , wherein the table lookup unit is configured to retrieve a subset of the first set of data to produce the second set of data. 
     
     
         15 . The device of  claim 10  further comprising a histogram unit coupled to the set of vector registers in parallel with the set of processing element and the table lookup unit. 
     
     
         16 . The device of  claim 1 , wherein the decoder is configured to:
 cause the first set of data to be stored in the set of vector registers; and   after the operation is performed on the first set of data, cause the second set of data to be stored in the set of vector registers.   
     
     
         17 . A method comprising:
 receiving a vector instruction that specifies:
 a first set of data stored in a memory using a set of loops; and 
 whether a set of processing elements or a table lookup unit coupled in parallel with the set of processing elements is to perform an operation on the first set of data; and 
   performing the operation on the first set of data to produce a second set of data.   
     
     
         18 . The method of  claim 17 , wherein:
 the vector instruction is a first vector instruction; and   the method further comprises receiving a second vector instruction that specifies the operation.   
     
     
         19 . The method of  claim 17 , wherein:
 the vector instruction specifies to perform the operation using the set of processing elements; and   the operation includes at least one of: bit interleaving, bit deinterleaving, conditional movement, conditional swap, sort, addition, logical AND, or logical OR.   
     
     
         20 . The method of  claim 17 , wherein:
 the vector instruction specifies to perform the operation using the table lookup unit; and   the operation includes copying a subset of the first set of data to produce the second set of data.