Three-dimensional semiconductor memory devices and methods of fabricating the same

Abstract

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;   a semiconductor pattern penetrating the stacked structure; and   a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes,   wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall,   wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns,   wherein the capping layer comprises a silicon oxide layer,   wherein the blocking insulation layer comprises a metallic material, and   wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the tunneling layer, the charge storage layer, and the capping layer surround a sidewall of the semiconductor pattern. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the capping layer extends along a sidewall of the semiconductor pattern in a first direction perpendicular to a top surface of the substrate. 
     
     
         4 . The semiconductor memory device of  claim 1 , wherein portions of the blocking insulation layer cover top and bottom surfaces of the electrodes. 
     
     
         5 . The semiconductor memory device of  claim 1 , wherein the blocking insulation layer further comprises:
 a second portion adjacent to a sidewall of the semiconductor pattern; and   third portions adjacent to top and bottom surfaces of the electrodes.   
     
     
         6 . The semiconductor memory device of  claim 5 , wherein the third portions of the blocking insulation layer contact top and bottom surfaces of the insulating patterns. 
     
     
         7 . The semiconductor memory device of  claim 5 , wherein the first, second, and third portions of the blocking insulation layer are continuously connected to each other. 
     
     
         8 . The semiconductor memory device of  claim 1 , wherein each of the electrodes includes a metal nitride layer and a tungsten pattern. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein:
 the tunneling layer comprises at least one silicon oxide layer; and   the charge storage layer comprises:
 an insulating layer with a higher density of trap sites than a silicon oxide layer; or 
 an insulating layer with intrinsic conductive nano particles. 
   
     
     
         10 . The semiconductor memory device of  claim 1 , wherein the blocking insulation layer comprises an aluminum oxide layer. 
     
     
         11 . A semiconductor memory device comprising:
 a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;   a vertical structure extending in a first direction perpendicular to a top surface of the substrate and penetrating the stacked structure, the vertical structure including a buried pattern, a channel layer, a tunneling layer, a charge storage layer, and a capping layer; and   a horizontal structure extending in a second direction parallel to the top surface of the substrate, the horizontal structure including a blocking insulation layer, a metal nitride layer, and a tungsten pattern,   wherein each of the insulating patterns has a first sidewall adjacent the vertical structure and a second sidewall opposite the first sidewall,   wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns, and   wherein a portion of the blocking insulation layer extends along the second sidewalls of the respective insulating patterns.   
     
     
         12 . The semiconductor memory device of  claim 11 ,
 wherein the horizontal structure surrounds the vertical structure, and   wherein the metal nitride layer and the tungsten pattern constitute each of the electrodes.   
     
     
         13 . The semiconductor memory device of  claim 11 ,
 wherein the channel layer surrounds a sidewall of the buried pattern, and   wherein the tunneling layer, the charge storage layer, and the capping layer surround a sidewall of the channel layer.   
     
     
         14 . The semiconductor memory device of  claim 11 , wherein the blocking insulation layer covers top and bottom surfaces of the metal nitride layer. 
     
     
         15 . The semiconductor memory device of  claim 11 , wherein the metal nitride layer covers top and bottom surfaces of the tungsten pattern. 
     
     
         16 . The semiconductor memory device of  claim 11 , wherein the horizontal structure is located between adjacent ones of the insulating patterns. 
     
     
         17 . The semiconductor memory device of  claim 11 ,
 wherein the capping layer comprises a silicon oxide layer, and   wherein the blocking insulation layer comprises an aluminum oxide layer.   
     
     
         18 . The semiconductor memory device of  claim 11 ,
 wherein the channel layer has a cylindrical shape, and   wherein the buried pattern is provided in the channel layer.   
     
     
         19 . A data storage system comprising:
 a plurality of semiconductor memory devices; and   a controller that is configured to control the semiconductor memory devices,   wherein each of the semiconductor memory devices comprises:
 a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate; 
 a semiconductor pattern penetrating the stacked structure; and 
 a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes, 
 wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall, 
 wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns, 
 wherein the capping layer comprises a silicon oxide layer, 
 wherein the blocking insulation layer comprises a metallic material, and 
 wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns. 
   
     
     
         20 . The data storage system of  claim 19 , wherein the blocking insulation layer comprises an aluminum oxide layer.