US2023031642A1PendingUtilityA1
Germanium-Silicon-Tin (GeSiSn) Heterojunction Bipolar Transistor Devices
Individually held — no corporate assignee on recordPriority: Mar 15, 2013Filed: Sep 26, 2022Published: Feb 2, 2023
Est. expiryMar 15, 2033(~6.6 yrs left)· nominal 20-yr term from priority
Inventors:Matthew H. Kim
H10D 62/832H10D 62/184H10D 10/881H10D 10/861H10D 10/841H10D 10/80H10D 62/8503H10D 62/822H10D 62/812H10D 62/177H10D 62/137H10D 62/136H10D 62/82H10D 10/821H10D 10/021H10H 20/00H10D 10/891H01S 5/06203H01S 5/3427H01S 5/0218H01S 5/3412H01S 5/0202H01S 5/0215H01S 5/18341H01S 5/22H01S 5/3407H01S 5/34353H01S 5/18305H01S 5/3211H01S 5/021H01L 29/0817H01L 29/7378H01L 29/267H01L 33/0004H01L 29/7371H01L 29/165H01L 29/2003H01L 29/122H01L 29/66242H01L 29/0821H01L 29/1004
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Claims
Abstract
A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing a transistor, the method comprising:
forming a GeSiSn base region; forming an emitter region; and forming a collector region, wherein:
the transistor is a NPN heterojunction bipolar transistor; and
the GeSiSn base region comprises a Sn content and a Si content to be latticed matched or coherently strained to GaAs.
2 . The method of claim 1 , further comprising wafer bonding the collector region comprising a GaN collector region to the GeSiSn base region.
3 . The method of claim 1 , further comprising wafer bonding the collector region comprising a SiC collector region to the GeSiSn base region.
4 . The method of claim 1 , wherein the emitter region comprises GaAs.
5 . The method of claim 1 , wherein the emitter region comprises InGaP.
6 . The method of claim 1 , wherein the emitter region comprises AlGaAs.
7 . The method of claim 2 , wherein the GaN collector region comprises a cubic GaN or wurtzite GaN.
8 . The method of claim 3 , wherein the SiC collector region comprises one of: a 3C SiC or 4H SiC or 6H SiC.
9 . A method of manufacturing a transistor, the method comprising:
forming a GeSi base region; forming an emitter region; and forming a collector region, wherein:
the transistor is a NPN heterojunction bipolar transistor; and
the GeSi base region comprises a Si content to be latticed matched or coherently strained to GaAs.
10 . The method of claim 9 , further comprising wafer bonding the collector region comprising a GaN collector region to the GeSi base region.
11 . The method of claim 9 , further comprising wafer bonding the collector region comprising a SiC collector region to the GeSi base region.
12 . The method of claim 9 , wherein the emitter region comprises GaAs.
13 . The method of claim 9 , wherein the emitter region comprises InGaP.
14 . The method of claim 9 , wherein the emitter region comprises AlGaAs.
15 . The method of claim 10 , wherein the GaN collector region comprises a cubic GaN or wurtzite GaN.
16 . The method of claim 11 , wherein the SiC collector region comprises one of: a 3C SiC or 4H SiC or 6H SiC.
17 . A method of manufacturing a transistor, the method comprising:
forming a GaAs base region; forming an InGaP emitter region; forming a GaAs emitter cap region; forming an emitter base stack, wherein the emitter base stack comprises the GaAs emitter cap region, the InGaP emitter region, and the GaAs base region; and forming a collector region, wherein:
the transistor is a NPN heterojunction bipolar transistor;
the InGaP emitter region comprises one of: an ordered phase or disordered phase or mixed phase;
the InGaP emitter region is lattice matched or near latticed matched to GaAs; and
the GaAs base region is wafer bonded to the collector region.
18 . The method of claim 17 , further comprising wafer bonding the collector region comprising a GaN collector region to the GaAs base region.
19 . The method of claim 17 , further comprising wafer bonding the collector region comprising a SiC collector region to the GaAs base region.
20 . The method of claim 17 , wherein the GaAs base region to the InGaP emitter region has a conduction band offset less than 0.2 eV.Join the waitlist — get patent alerts
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