Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same
Abstract
An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A fan-out silicon interposer comprising:
a bridge die including an array of through-silicon via (TSV) structures extending through a silicon substrate and comprising metal pads; through-integrated-fan-out via (TIV) structures located aside the bridge die; an encapsulant that laterally surrounds the bridge die and the TIV structures; a first redistribution structure located on the bridge die; and a second redistribution structure located at an opposite side of the first redistribution structure relative to the bridge die, wherein the metal pads are located between the array of TSV structures and the second redistribution structure.
2 . The fan-out silicon interposer of claim 1 , wherein the TIV structures vertically extend through the encapsulant and electrically connects a respective first redistribution wiring interconnect in the first redistribution structure to a respective second redistribution wiring interconnect in the second redistribution structure.
3 . The fan-out silicon interposer of claim 1 , wherein the bridge die comprises metal interconnect structures electrically connecting a respective one of the TSV structures and a respective one of the metal pads.
4 . The fan-out silicon interposer of claim 3 , wherein the metal interconnect structures comprise a combination of metal line structures and metal via structures, or integrated metal line and via structures.
5 . The fan-out silicon interposer of claim 1 , wherein the bridge die comprises additional metal pads contacting an end surface of a respective one of the TSV structures and having a greater width than the end surface of the respective one of the TSV structures.
6 . The fan-out silicon interposer of claim 5 , wherein a horizontal plane including interfaces between the additional metal pads and the TSV structures is more proximal to the second redistribution structure than a horizontal plane including an interface between the encapsulant and the first redistribution structure is to the second redistribution structure.
7 . The fan-out silicon interposer of claim 5 , wherein a horizontal plane including interfaces between the additional metal pads and the TSV structures is more proximal to the second redistribution structure than a horizontal plane including interfaces between the TIV structures and the first redistribution structure is to the second redistribution structure.
8 . The fan-out silicon interposer of claim 5 , wherein interfaces between the TIV structures and the second redistribution structure are located within a same horizontal plane as interfaces between the metal pads and the second redistribution structure.
9 . The fan-out silicon interposer of claim 5 , wherein:
each of the TSV structures is laterally surrounded by a respective cylindrical portion of a through-substrate insulating spacer; and the silicon substrate is vertically spaced from a horizontal plane including interfaces between the additional metal pads and the TSV structures by a backside insulating layer that laterally surrounds the cylindrical portions of the through-substrate insulating spacer.
10 . A fan-out silicon interposer comprising:
a bridge die including an array of through-silicon via (TSV) structures extending through a silicon substrate, first metal pads contacting first end surfaces of the array of TSV structures, and a first dielectric material layer that laterally surrounds the first metal pads; an encapsulant that laterally surrounds the bridge die; a first redistribution structure comprising first redistribution wiring interconnects that contact the first metal pads with a non-zero alignment overlay; and a second redistribution structure including second metal pads and located at an opposite side of the first redistribution structure relative to the bridge die.
11 . The fan-out silicon interposer of claim 10 , wherein one of the first metal pads contacts an end surface of a respective one of the TSV structures and has a greater horizontal cross-sectional area than the end surface of the respective one of the TSV structures.
12 . The fan-out silicon interposer of claim 10 , wherein a horizontal plane including interfaces between the first metal pads and the TSV structures is more proximal to the second redistribution structure than a horizontal plane including an interface between the encapsulant and the first redistribution structure is to the second redistribution structure.
13 . The fan-out silicon interposer of claim 10 , further comprising through-integrated-fan-out via (TIV) structures that vertically extends through the encapsulant and electrically connecting a respective first redistribution wiring interconnect in the first redistribution structure to a respective second redistribution wiring interconnect in the second redistribution structure.
14 . The fan-out silicon interposer of claim 13 , wherein a horizontal plane including interfaces between the first metal pads and the first redistribution structure is more proximal to the second redistribution structure than the horizontal plane including the interfaces between the TIV structures and the first redistribution structure is to the second redistribution structure.
15 . The fan-out silicon interposer of claim 10 , wherein the bridge die comprises metal interconnect structures providing electrically connection between a respective one of the TSV structures and respective one of the second metal pads.
16 . The fan-out silicon interposer of claim 10 , wherein:
the second pads comprises an array of microbumps; and the first redistribution structure comprises first bonding pads that include an array of C4 bonding pads, wherein the first bonding pads are electrically connected to a respective one of the first metal pads through first redistribution wiring interconnects in the first redistribution structure.
17 . A fan-out silicon interposer comprising:
a bridge die including an array of through-silicon via (TSV) structures extending through a silicon substrate, first metal pads contacting first end surfaces of the array of TSV structures, and a first dielectric material layer that laterally surrounds the first metal pads; an encapsulant that laterally encapsulates the bridge die and the first metal pads; a first redistribution structure located on the first metal pads and contacting the first dielectric material layer of the bridge die; and a second redistribution structure including second bonding pads and located at an opposite side of the first redistribution structure relative to the bridge die.
18 . The fan-out silicon interposer of claim 1 , wherein each of the first metal pads contacts an end surface of a respective one of the TSV structures and has a greater horizontal cross-sectional area than the end surface of the respective one of the TSV structures.
19 . The fan-out silicon interposer of claim 18 , wherein a sidewall of the first dielectric material layer is in direct contact with the encapsulant.
20 . The fan-out silicon interposer of claim 18 , wherein the first redistribution structure comprises first redistribution wiring interconnects that contact the first metal pads with a non-zero alignment overlay.Join the waitlist — get patent alerts
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