Semiconductor devices and methods of designing and manufacturing the same

Abstract

A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first conductive region having a first width and extending along a first direction;   a second conductive region having a second width and extending along the first direction, the first width greater than the second width;   a first active region having a third width and extending along the first direction;   a second active region having a fourth width and extending along the first direction, the third width less than the fourth width; and   a third conductive region extending along a second direction and electrically connected to the first conductive region, the second direction different from the first direction,   wherein the first and second active regions are neighboring active regions.   
     
     
         2 . The semiconductor device of  claim 1 , wherein:
 the first conductive region is in a first layer;   the third conductive region is in a second layer; and   the second direction is perpendicular to the first direction.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a via coupled between the first conductive region and the third conductive region, the via having a fifth width equal to or less than the first width.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a third active region having the fourth width, extending along the first direction, and coupled to the first active region.   
     
     
         5 . The semiconductor device of  claim 1 , wherein a space between the third conductive region and the first active region is equal to or greater than a threshold of space. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a fourth conductive region having the second width and extending along the first direction;   wherein:
 the first, second, and fourth conductive regions are in a first layer; and 
 the third conductive region is in a second layer and extends along the second direction perpendicular to the first direction. 
   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a fourth conductive region extending along the second direction; and   an isolating region extending along the second direction and formed between the third and fourth conductive regions.   
     
     
         8 . The semiconductor device of  claim 7 , wherein:
 the first and second active regions are in a first layer;   the third and fourth conductive regions and the isolating region are in a second layer, the second layer different from the first layer;   the third conductive region extends in the second layer and above the second active region in the first layer; and   the fourth conductive region extends in the second layer and above the first active region in the first layer.   
     
     
         9 . The semiconductor device of  claim 7 , wherein the isolating region is a first isolating region, the semiconductor device further comprising:
 a second isolating region extending along the second direction,   wherein:
 the first and second isolating regions are on opposite sides of the first active region; and 
 a distance between the first and second isolating regions is equal to or greater than a threshold distance. 
   
     
     
         10 . The semiconductor device of  claim 1 , further comprising:
 a first via coupled between the first conductive region and the third conductive region; and   a second via coupled to a source of a transistor,   wherein the first and second vias are on opposite sides of the first active region.   
     
     
         11 . The semiconductor device of  claim 1 , further comprising:
 a fourth conductive region having the first width and extending along the first direction;   a fifth conductive region having the second width and extending along the first direction;   a third active region having the third width and extending along the first direction;   a fourth active region having the fourth width and extending along the first direction; and   a sixth conductive region extending along the second direction and electrically connected to the fourth conductive region,   wherein the third and fourth active regions are neighboring active regions.   
     
     
         12 . The semiconductor device of  claim 11 , wherein:
 the third and sixth conductive regions are on opposite sides of the first active region; and   the third and sixth conductive regions are on opposite sides of the third active region.   
     
     
         13 . The semiconductor device of  claim 11 , further comprising:
 a first via coupled between the first conductive region and the third conductive region;   a second via coupled between the fourth conductive region and the sixth conductive region; and   a third via coupled to a source of a transistor;   wherein the second and third vias are on opposite sides of the third active region.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the transistor is a first transistor, the semiconductor device further comprising:
 a fourth via coupled to a source of a second transistor,   wherein the first and fourth vias are on opposite sides of the first active region.   
     
     
         15 . A flip-flop circuit, comprising:
 a first conductive region having a first width and extending along a first direction;   a second conductive region having a second width and extending along the first direction, the first width greater than the second width;   an active region having a third width and a fourth width, and extending along the first direction, the third width less than the fourth width; and   a third conductive region extending along a second direction and electrically connected to the first conductive region, the second direction different from the first direction.   
     
     
         16 . The flip-flop circuit of  claim 15 , wherein:
 the first, second, and third conductive regions and the active region are a first plurality of circuits; and   the flip-flop circuit further comprises a second plurality of circuits comprising a longest circuit path of the flip-flop circuit.   
     
     
         17 . The flip-flop circuit of  claim 15 , further comprising:
 a multiplexer comprising a data input circuit and a scan input circuit,   wherein the scan input circuit comprises at least a part of the first active region.   
     
     
         18 . A method for fabricating an integrated circuit, the method comprising:
 forming a first active region in a first layer, the first active region having a first width and extending along a first direction;   forming a second active region in the first layer, the second active region having a second width and extending along the first direction, the first width less than the second width;   wherein the first and second active regions are neighboring active regions;   forming an isolating region in a second layer, the second layer being above the first layer;   forming a first conductive region in the second layer, the first conductive region extending along a second direction, the second direction different from the first direction;   fabricating a via coupled to the first conductive region and above the second layer, the via having a third width;   forming a second conductive region in a third layer and coupled to the via, the third layer being above the second layer, the via coupled between the first conductive region in the second layer and the second conductive region in the third layer, the second conductive region having a fourth width and extending along the first direction, the third width equal to or less than the fourth width; and   forming a third conductive region in the third layer, the third conductive region having a fifth width and extending along the first direction, the fourth width greater than the fifth width.   
     
     
         19 . The method of  claim 18 , further comprising:
 forming a third active region in the first layer, the third active region having the second width, extending along the first direction, and coupled to the first active region.   
     
     
         20 . The method of  claim 18 , wherein the isolation region is a first isolation region, the method further comprising:
 forming a second isolating region in the second layer;   wherein:
 the first and second isolating regions are on opposite sides of the first active region; and 
 a distance between the first and second isolating regions is equal to or greater than a threshold distance.