US2023012200A1PendingUtilityA1

Shaped interconnect bumps in semiconductor devices

Assignee: TEXAS INSTRUMENTS INCPriority: Oct 5, 2017Filed: Sep 13, 2022Published: Jan 12, 2023
Est. expiryOct 5, 2037(~11.2 yrs left)· nominal 20-yr term from priority
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Claims

Abstract

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of forming a semiconductor package, the method comprising:
 depositing a seed material on a wafer;   depositing a photoresist on the seed material;   masking the photoresist according to a pattern with bump sites;   overexposing the masked photoresist to form a plurality of tapered sites therein, each tapered site having a first end closest to the wafer and a second end further from the wafer;   disposing one or more metals into the plurality of tapered sites;   removing the photoresist to form a plurality of tapered bumps, wherein each tapered bump of the plurality of tapered bumps has a first surface area a1 at a first end closest to the wafer and has a second end surface area a2 at a second end further from the wafer, wherein the first end of the tapered bump abuts the wafer and wherein the first surface area a1 is less than the second surface area a2;   singulating the wafer into a plurality of dies; and   mounting a die of the plurality of dies on a leadframe.   
     
     
         2 . The method of  claim 1 , wherein the second end surface area a2 is at 10 percent greater than the first surface area a1. 
     
     
         3 . The method of  claim 1 , wherein the second surface area a2 is at least twice the first surface area a1. 
     
     
         4 . The method of  claim 1 , wherein each of the plurality of tapered sites is formed with sidewall slope of approximately 70 degrees or less with respect to a surface of the die facing the leadframe. 
     
     
         5 . The method of  claim 1 , wherein each of the plurality of tapered bumps has a lateral cross section with a curvilinear shape. 
     
     
         6 . The method of  claim 5 , wherein each of the plurality of tapered bumps has a lateral cross section with circular or oval shape. 
     
     
         7 . The method of  claim 1  further comprising covering portions of the die, the leadframe, and the plurality of tapered bumps using a mold compound. 
     
     
         8 . The method of  claim 1 , wherein mounting the die on the leadframe includes making electrical connections between the die and the leadframe. 
     
     
         9 . A method of electrically coupling a semiconductor die to a leadframe, the method comprising:
 forming a plurality of tapered bumps on the die, such that each of the plurality of tapered bumps has a first end surface area a1 at a first end closest to the die and a second end surface area a2 at a second opposing end, wherein the first end surface area a1 is less than the second end surface area a2, and wherein the first end is attached to the die; and   soldering the second end of the plurality of tapered bumps to the leadframe.   
     
     
         10 . The method of  claim 9 , wherein the second end surface area a2 is at least twice the first end surface area a  1 . 
     
     
         11 . The method of  claim 9 , wherein the plurality of tapered sites has a sidewall slope of approximately 70 degrees or less with respect to a centerline of the tapered site. 
     
     
         12 . The method of  claim 9 , wherein each of the plurality of tapered bumps has an oval shape in a lateral cross section that is orthogonal to a centerline of the tapered bump. 
     
     
         13 . The method of  claim 9  further comprising covering portions of the die, the leadframe, and the plurality of tapered bumps using a mold compound. 
     
     
         14 . The method of  claim 9 , wherein the leadframe is metallic. 
     
     
         15 . The method of  claim 9 , wherein the plurality of bumps is comprised of copper.

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