Semiconductor device and method of manufacturing thereof

Abstract

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

1 . A semiconductor device, comprising:
 a first semiconductor element having a first electrode;   a second semiconductor element having a second electrode;   a Sn-based micro-solder bump formed on the second electrode; and   a concave bump pad formed on the first electrode opposite to the micro-solder bump,   wherein the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a second metal layer and a third metal layer that are sequentially formed on the concave bump pad,
 wherein the third metal layer is diffused to the micro-solder bump, and   wherein the second metal layer is made of a metal of the vanadium group.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein the first semiconductor element has a plurality of concave bump pads thereon, the diameters of which are different from each other. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein the diameters of the concave bump pads differ depending on the use of the respective electrodes connected thereto. 
     
     
         5 . The semiconductor device according to  claim 2 , wherein a diameter of the micro-solder bump corresponds to a diameter of the concave bump pad. 
     
     
         6 . The semiconductor device according to  claim 2 , further comprising a first metal layer that is sequentially formed on the concave bump pad together with the second metal layer and the third metal layer, wherein the third metal layer is closest to the micro-solder bump, and wherein the first metal layer is a nitride film of the metal of the vanadium group used in the second metal layer. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein the second metal layer has an average thickness of 30 nanometers or greater. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein the first metal layer has an average thickness of 10 nanometers or greater. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the second metal layer is Ta, and the first metal layer is TaN. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the third metal layer is one of Cu, Co, Ni, Pd, Au, and Pt. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the first electrode is a through-electrode. 
     
     
         12 . The semiconductor device according to  claim 1 , further comprising:
 an opening portion that extends from a surface of the first semiconductor element to a metal wiring in the first semiconductor element,   wherein the opening portion forms the concave bump pad.   
     
     
         13 . The semiconductor device according to  claim 1 , wherein the semiconductor device is a stacked CMOS image sensor including a logic chip equivalent to the second semiconductor element that is CoW-connected to a pixel substrate equivalent to the first semiconductor element. 
     
     
         14 . A method of manufacturing a semiconductor device that includes a first semiconductor element having a first electrode stacked with a second semiconductor element having a second electrode, the method comprising:
 forming a Sn-based micro-solder bump on the second electrode; and   forming a concave bump pad on the first electrode opposite to the micro-solder bump,   wherein the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.   
     
     
         15 . The manufacturing method according to  claim 14 , wherein during the forming of the concave bump pad, a second metal layer made of a metal of the vanadium group is formed on the first electrode and a third metal layer is formed on the second metal layer, wherein the third metal layer is diffused to the micro-solder bump, and the micro-solder bump and the third metal layer are subjected to a heating treatment with a reducing atmosphere, and thereby the third metal layer and an oxide film on the surface of the micro-solder bump are reduced, and due to the diffusion of the third metal layer to the micro-solder bump, the micro-solder bump and the second metal layer are brought into contact with each other, and the first and second electrodes are electrically connected to each other. 
     
     
         16 . The manufacturing method according to  claim 15 , wherein during the forming of the concave bump pad, a passivation layer is formed on the third metal layer of the first semiconductor element, and an opening portion is formed via etching of the passivation layer to expose the third metal layer. 
     
     
         17 . The manufacturing method according to  claim 15 , wherein during the forming of the concave bump pad, before the second metal layer is formed, a first metal layer is formed on the first electrode, and wherein the first electrode is connected to the second semiconductor element via the micro-solder bump, and the first metal layer is a nitride film of the metal of the vanadium group used in the second metal layer. 
     
     
         18 . The manufacturing method according to  claim 14 , wherein the first electrode is a through-electrode. 
     
     
         19 . The manufacturing method according to  claim 14 , wherein during the forming of the concave bump pad, the concave bump pad is formed by providing an opening portion from a surface of the first semiconductor element to a metal wiring in the first semiconductor element. 
     
     
         20 . The manufacturing method according to  claim 14 , wherein the semiconductor device is a stacked CMOS image sensor including a logic chip equivalent to the second semiconductor element and a pixel substrate equivalent to the first semiconductor element, and wherein the logic chip and the pixel substrate are subjected to a heat treatment while the concave bump pad and the micro-solder bump are in contact.