US2023005807A1PendingUtilityA1
Zinc Layer For A Semiconductor Die Pillar
Est. expiryOct 5, 2037(~11.2 yrs left)· nominal 20-yr term from priority
H10W 72/0198H10W 90/701H10W 90/00H10W 74/129H10W 74/014H10W 72/20H10W 72/012H10W 70/635H10W 70/614H10W 70/611H10W 70/093H10W 70/09H10W 72/952H10W 72/29H10W 72/019H10W 72/01938H10W 72/072H10W 72/241H10W 90/724H10W 72/253H10W 72/252H10W 72/222H10W 72/01265H10W 72/01235H10W 72/01251H10W 72/01255H10W 74/117H01L 21/561H01L 24/82H01L 2224/94H01L 24/13H01L 2924/15313H01L 24/11H01L 24/19H01L 23/5384H01L 24/17H01L 23/3114H01L 25/0657H01L 23/49811H01L 23/5389H01L 23/3128
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Claims
Abstract
A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) in contact with the via; and a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW, the copper pillar including zinc within the bottom portion.
2 . The semiconductor device of claim 1 , wherein the layer of TiW contacts portions of the semiconductor die.
3 . The semiconductor device of claim 1 , wherein the via includes copper.
4 . The semiconductor device of claim 1 , wherein a lateral width of the layer of TiW is more than a lateral width of the via.
5 . The semiconductor device of claim 1 further including mold compound in contact with the semiconductor die, the layer of TiW, and the copper pillar.
6 . The semiconductor device of claim 1 , wherein the via includes copper.
7 . A packaged semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) coupled to the via; a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW; a substrate coupled to the copper pillar; and molding compound covering portions of the semiconductor die, the copper pillar, the layer of TiW, and the substrate.
8 . The packaged semiconductor device of claim 7 , wherein the layer of TiW contacts portions of the semiconductor die.
9 . The packaged semiconductor device of claim 7 , wherein the via includes copper.
10 . The packaged semiconductor device of claim 7 , wherein the copper pillar includes interdiffused zinc within the bottom portion.
11 . A semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) in contact with the via; and a copper pillar including a top portion and a bottom portion, the bottom portion in contact with the layer of TiW.
12 . The semiconductor device of claim 11 , wherein the layer of TiW contacts portions of the semiconductor die.
13 . The semiconductor device of claim 11 , wherein the via includes copper.
14 . The semiconductor device of claim 11 , wherein a lateral width of the layer of TiW is more than a lateral width of the via.
15 . The semiconductor device of claim 11 further including mold compound in contact with the semiconductor die, the layer of TiW, and the copper pillar.
16 . The semiconductor device of claim 11 , wherein the via includes copper.
17 . The packaged semiconductor device of claim 11 , wherein the copper pillar includes zinc within the bottom portion.
18 . The packaged semiconductor device of claim 17 , wherein the zinc is interdiffused zinc.Join the waitlist — get patent alerts
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