Nand raid controller

Abstract

An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. The array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.

1 . A controller connectable between a semiconductor processor and a plurality of memory devices including a first and a second memory devices, the controller comprising:
 an enable input configured to connect to an enable output of the semiconductor processor;   a data input configured to connect to a data output of the semiconductor processor;   a buffer configured to store write data to be written to at least the first or second memory devices, and information according to a storage location of the first or second memory devices to which the write data is to be written;   a data output configured to connect to a data input of each of the first and second memory devices;   a first enable output configured to connect to an enable input of the first memory device; and   a second enable output configured to connect to an enable input of the second memory device,   wherein in response to the enable input of the controller being asserted, the controller is configured to:   receive the information according to the storage location from the semiconductor processor,   store the received information into the buffer, and   assert one of the first and second enable outputs on the basis of the enable input being asserted and the stored information.   
     
     
         2 . The controller according to  claim 1 , wherein the information according to the storage location identifies one of the first and second memory devices. 
     
     
         3 . The controller according to  claim 1 , wherein the controller is further configured to:
 receive a command designating to write the write data from the semiconductor processor,   store the received command into the buffer, and   assert the one of the first and second enable outputs also on the basis of the stored command.   
     
     
         4 . The controller according to  claim 3 , wherein the controller is further configured to transmit, to the one of the first and second memory devices identified by the stored information via the data output, a command and address information on the basis of the stored information and the stored command, the address information specifying the storage location of the one of the first and second memory devices identified by the stored information. 
     
     
         5 . The controller according to  claim 4 , wherein the controller is further configured to:
 receive the write data from the semiconductor processor; and   store the received write data into the buffer.   
     
     
         6 . The controller according to  claim 5 , wherein the controller is further configured to transmit, to the one of the first and second memory devices identified by the stored information via the data output, the write data stored in the buffer. 
     
     
         7 . The controller according to  claim 1 , wherein the controller is further configured to:
 receive the write data from the semiconductor processor; and   store the received write data into the buffer.   
     
     
         8 . The controller according to  claim 7 , wherein the controller is further configured to transmit, to the one of the first and second memory devices identified by the stored information via the data output, the write data stored in the buffer. 
     
     
         9 . The controller according to  claim 1 , wherein
 the plurality of memory devices further includes a third memory device,   the controller further comprises a third enable output configured to connect to an enable input of the third memory device, and   the data output is configured to connect to a data input of the third memory device.   
     
     
         10 . The controller according to  claim 9 , wherein in response to the enable input of the controller being asserted, the controller is configured to assert two of the first, second, and third enable outputs on the basis of the enable input being asserted and the stored information. 
     
     
         11 . A method performed by a controller connectable between a semiconductor processor and a plurality of memory devices including a first and a second memory devices, the controller comprising:
 an enable input configured to connect to an enable output of the semiconductor processor;   a data input configured to connect to a data output of the semiconductor processor;   a buffer configured to store write data to be written to at least the first or second memory devices, and information according to a storage location of the first or second memory devices to which the write data is to be written;   a data output configured to connect to a data input of each of the first and second memory devices;   a first enable output configured to connect to an enable input of the first memory device; and   a second enable output configured to connect to an enable input of the second memory device,   the method comprising:   in response to the enable input of the controller being asserted,   receiving the information according to the storage location from the semiconductor processor;   storing the received information into the buffer; and   asserting one of the first and second enable outputs on the basis of the enable input being asserted and the stored information.   
     
     
         12 . The method according to  claim 11 , wherein the information according to the storage location identifies one of the first and second memory devices. 
     
     
         13 . The method according to  claim 11 , further comprising:
 receiving a command designating to write the write data from the semiconductor processor;   storing the received command into the buffer; and   asserting the one of the first and second enable outputs also on the basis of the stored command.   
     
     
         14 . The method according to  claim 13 , further comprising:
 transmitting, to the one of the first and second memory devices identified by the stored information via the data output, a command and address information on the basis of the stored information and the stored command, the address information specifying the storage location of the one of the first and second memory devices identified by the stored information.   
     
     
         15 . The method according to  claim 14 , further comprising:
 receiving the write data from the semiconductor processor; and   storing the received write data into the buffer.   
     
     
         16 . The method according to  claim 15 , further comprising:
 transmitting, to the one of the first and second memory devices identified by the stored information via the data output, the write data stored in the buffer.   
     
     
         17 . The method according to  claim 11 , further comprising:
 receiving the write data from the semiconductor processor; and   storing the received write data into the buffer.   
     
     
         18 . The method according to  claim 17 , further comprising:
 transmitting, to the one of the first and second memory devices identified by the stored information via the data output, the write data stored in the buffer.   
     
     
         19 . The method according to  claim 11 , wherein
 the plurality of memory devices further includes a third memory device,   the controller further comprises a third enable output configured to connect to an enable input of the third memory device, and   the data output is configured to connect to a data input of the third memory device.   
     
     
         20 . The method according to  claim 19 , further comprising:
 in response to the enable input of the controller being asserted, asserting two of the first, second, and third enable outputs on the basis of the enable input being asserted and the stored information.