US2022416072A1PendingUtilityA1

Nitride semiconductor device and method of manufacturing the same

Assignee: ROHM CO LTDPriority: Nov 30, 2018Filed: Aug 31, 2022Published: Dec 29, 2022
Est. expiryNov 30, 2038(~12.3 yrs left)· nominal 20-yr term from priority
H01L 29/66462H01L 29/7787H01L 29/66431H01L 29/2003H10D 62/8503H10D 30/015H10D 64/64H10D 30/675H10D 30/6738H10D 64/111H10D 62/343H10D 30/4755H10D 30/475
70
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

There is provided a nitride semiconductor device that includes a first nitride semiconductor layer configured as an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer, a ridge-shaped nitride semiconductor gate layer disposed on the second nitride semiconductor layer and including an acceptor-type impurity, and a gate electrode formed on the nitride semiconductor gate layer. The gate electrode includes a first metal film that is formed on the nitride semiconductor gate layer and is mainly made of Ti, and a second metal film that is formed on the first metal film and is made of TiN.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A nitride semiconductor device comprising:
 a first nitride semiconductor layer configured as an electron transit layer;   a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer;   a source electrode;   a drain electrode;   a ridge-shaped nitride semiconductor gate layer disposed on the second nitride semiconductor layer and including an acceptor-type impurity;   a gate electrode formed on the nitride semiconductor gate layer and configured to control electric conduction between the source electrode and the drain electrode;   an insulating layer configured to cover opposite end portions of an upper surface of the nitride semiconductor gate layer, and a side surface and an upper surface of the gate electrode; and   a SiN layer configured to cover the nitride semiconductor gate layer and the insulating layer,   wherein the gate electrode includes TiN.   
     
     
         2 . The nitride semiconductor device of  claim 1 , wherein the nitride semiconductor gate layer comprises only a third nitride semiconductor layer containing an acceptor-type impurity. 
     
     
         3 . The nitride semiconductor device of  claim 1 , wherein the nitride semiconductor gate layer includes:
 a third nitride semiconductor layer that is formed on the second nitride semiconductor layer and contains an acceptor-type impurity, and   a fourth nitride semiconductor layer that is stacked on the third nitride semiconductor layer and has a hole concentration lower than a hole concentration of the third nitride semiconductor layer.   
     
     
         4 . The nitride semiconductor device of  claim 3 , wherein the fourth nitride semiconductor layer contains a donor-type impurity. 
     
     
         5 . The nitride semiconductor device of  claim 1 , wherein the insulating layer is SiN, SiO 2 , SiON or a composite layer thereof. 
     
     
         6 . The nitride semiconductor device of  claim 1 , wherein
 insulating layer is SiN, SiO 2 , SiON, or a composite layer thereof, and   the SiN layer is SiN, SiO 2 , SiON, or a composite layer thereof.   
     
     
         7 . The nitride semiconductor device of  claim 1 ,
 wherein the gate electrode includes:
 a first metal film that is formed on the nitride semiconductor gate layer, and 
 a second metal film that is formed on the first metal film, and 
   wherein the first metal film has:
 a first region made of TiN, which is a surface layer portion on a side of the nitride semiconductor gate layer, and 
 a second region made of Ti other than the first region. 
   
     
     
         8 . The nitride semiconductor device of  claim 7 ,
 wherein the second metal film is made of TiN, and   wherein a Ti/N composition ratio of the first region is larger than a Ti/N composition ratio of the second metal film.   
     
     
         9 . The nitride semiconductor device of  claim 1 , wherein the SiN layer is configured to cover the gate electrode. 
     
     
         10 . The nitride semiconductor device of  claim 1 , wherein the SiN layer is a passivation layer. 
     
     
         11 . The nitride semiconductor device of  claim 1 , wherein the nitride semiconductor gate layer includes a GaN layer. 
     
     
         12 . The nitride semiconductor device of  claim 11 , wherein the acceptor-type impurity included in the nitride semiconductor gate layer is Mg.

Join the waitlist — get patent alerts

Track US2022416072A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.