Integration of a passive component in a cavity of an integrated circuit package

Abstract

A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

What is claimed is: 
     
         1 . A method of making a semiconductor package, comprising:
 etching a conductive member to form a leadframe;   etching the leadframe to form a cavity;   attaching a passive component to the leadframe inside the cavity; and   attaching the semiconductor die to the leadframe on a side of the leadframe opposite the cavity.   
     
     
         2 . The method of  claim 1 , wherein a height of the passive component is less than a depth of the cavity. 
     
     
         3 . The method of  claim 1 , wherein the leadframe has a thickness of T, and etching the leadframe to form the cavity includes etching the leadframe to a depth of approximately 75% of T. 
     
     
         4 . The method of  claim 1 , further comprising etching a recess in the cavity to electrically isolate terminals of the passive component. 
     
     
         5 . The method of  claim 4 , further comprising filling the recess with a pre-mold compound. 
     
     
         6 . The method of  claim 1 , further comprising molding that covers portions of the semiconductor die, the lead frame, the cavity, and the passive component with a mold compound. 
     
     
         7 . The method of  claim 6 , wherein a bottom surface of the passive component is not covered with mold compound. 
     
     
         8 . The method of  claim 1 , wherein the passive component is a capacitor. 
     
     
         9 . A method of making a semiconductor package, comprising:
 etching a conductive member to form a leadframe;   etching the leadframe to form a cavity;   attaching a passive component to the leadframe inside the cavity; and   attaching the semiconductor die to the leadframe on a side of the leadframe where the cavity is located.   
     
     
         10 . The method of  claim 9 , wherein a height of the passive component is less than a depth of the cavity. 
     
     
         11 . The method of  claim 9 , wherein the leadframe has a thickness of T, and etching the leadframe to form the cavity includes etching the leadframe to a depth of approximately 75% of T. 
     
     
         12 . The method of  claim 9 , further comprising etching a recess in the cavity to electrically isolate terminals of the passive component. 
     
     
         13 . The method of  claim 12 , further comprising filling the recess with a pre-mold compound. 
     
     
         14 . The method of  claim 9 , further comprising molding that covers portions of the semiconductor die, the lead frame, the cavity, and the passive component with a mold compound. 
     
     
         15 . The method of  claim 14 , wherein a bottom surface of the passive component is not covered with mold compound. 
     
     
         16 . The method of  claim 9 , wherein the passive component is a capacitor. 
     
     
         17 . The method of  claim 9 , wherein the passive component and the semiconductor die are on the same side of the leadframe.