Conditional Drift Cancellation Operations in Programming Memory Cells to Store Data

Abstract

A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.

What is claimed is: 
     
         1 . A device, comprising:
 a memory cell programmable to have a threshold voltage representative of predetermined data; and   a logic circuit configured to:
 make a determination to skip a drift cancellation pulse to the memory cell prior to applying a programming pulse to the memory cell, in response to a command to store the predetermined data in the memory cell; and 
 program, based on the determination, the memory cell using the programming pulse according to the predetermined data without applying the drift cancellation pulse; 
   wherein in absence of the determination, the logic circuit is configured to apply the drift cancellation pulse to the memory cell before programming the memory cell using the programming pulse.   
     
     
         2 . The device of  claim 1 , further comprising:
 a first voltage driver connected to the memory cell; and   a second voltage driver connected to the memory cell;   wherein the threshold voltage of the memory cell is programmable to be in a first state via the first voltage driver and the second voltage driver driving a first voltage pulse on the memory cell in a first polarity in which a voltage driven by the first voltage driver is higher than a voltage driven by the second voltage driver; and   wherein the drift cancellation pulse includes a second voltage pulse on the memory cell in a second polarity, opposite to the first polarity; and   wherein a voltage driven by the first voltage driver is lower than a voltage driven by the second voltage driver in the second polarity.   
     
     
         3 . The device of  claim 2 , wherein the determination to skip the drift cancellation pulse is based on an attribute of the memory cell. 
     
     
         4 . The device of  claim 3 , wherein the attribute of the memory cell is based at least in part on a location of the memory cell in the device. 
     
     
         5 . The device of  claim 3 , wherein the attribute of the memory cell is based at least in part on an address of the memory cell in the device. 
     
     
         6 . The device of  claim 3 , wherein the attribute of the memory cell is based at least in part on an indicator of an electrical distance from the memory cell to the first voltage driver and the second voltage driver. 
     
     
         7 . The device of  claim 3 , wherein the attribute of the memory cell is based on a time range within which the memory cell is previously applied a voltage pulse to store data. 
     
     
         8 . The device of  claim 3 , wherein the determination to skip the drift cancellation pulse is based on whether the first state is a pre-selected state. 
     
     
         9 . The device of  claim 8 , wherein the drift cancellation pulse is applied without the determination to skip the drift cancellation pulse based on the attribute, when the first state is an alternative state different from the pre-selected state. 
     
     
         10 . The device of  claim 9 , wherein in the first polarity, the first voltage driver is configured to drive a positive voltage relative to ground, and the second voltage driver configured to drive a negative voltage relative to the ground; in the second polarity, the first voltage driver is configured to drive a negative voltage relative to the ground, and the second voltage driver configured to drive a positive voltage relative to the ground; in driving the first voltage pulse, the first voltage driver and the second voltage driver are configured to drive voltages up to a first predetermined magnitude; and in driving the second voltage pulse when the first state is the pre-selected state, the first voltage driver and the second voltage driver are configured to drive voltages up to the first predetermined magnitude. 
     
     
         11 . The device of  claim 10 , wherein the logic circuit is further configured to instruct, in response to the determination to skip the drift cancellation pulse, the first voltage driver and the second voltage driver a third voltage pulse in the first polarity to determine whether a current going through the memory cell during the third voltage pulse is above a predetermined threshold. 
     
     
         12 . The device of  claim 11 , wherein response to the current being above the predetermined threshold during the third voltage pulse, the device is configured to skip the first voltage pulse following the third voltage pulse. 
     
     
         13 . The device of  claim 11 , wherein in driving the third voltage pulse, the first voltage driver and the second voltage driver are configured to drive voltages up to a second predetermined magnitude that is lower than the first predetermined magnitude; and the logic circuit is further configured to instruct, response to the current being below the predetermined threshold during the third voltage pulse, the first voltage driver and the second voltage driver to change from driving voltages up to the second predetermined magnitude to driving voltages up to the first predetermined magnitude without stopping driving voltages. 
     
     
         14 . A method, comprising:
 receiving, in a logic circuit, a command to store predetermined data in a memory cell that is programmable to have a threshold voltage representative of the predetermined data;   making, by the logic circuit, a determination to skip a drift cancellation pulse to the memory cell prior to applying a programming pulse to the memory cell, wherein in absence of the determination, the logic circuit is configured to apply the drift cancellation pulse to the memory cell before programming the memory cell using the programming pulse; and   programming, based on the determination, the memory cell using the programming pulse according to the predetermined data without applying the drift cancellation pulse.   
     
     
         15 . The method of  claim 14 , wherein the threshold voltage of the memory cell is programmable to be in a first state via a first voltage driver and a second voltage driver driving a first voltage pulse on the memory cell in a first polarity in which a voltage driven by the first voltage driver is higher than a voltage driven by the second voltage driver; and
 wherein the drift cancellation pulse includes a second voltage pulse on the memory cell in a second polarity, opposite to the first polarity; and   wherein a voltage driven by the first voltage driver is lower than a voltage driven by the second voltage driver in the second polarity.   
     
     
         16 . The method of  claim 15 , wherein the determination to skip the drift cancellation pulse is based on an attribute of the memory cell. 
     
     
         17 . The method of  claim 16 , wherein the attribute is based at least in part on a location of the memory cell, an address of the memory cell, an electrical distance from the memory cell to the two voltage drivers, or a timing of a command to store data into the memory cell, or any combination thereof. 
     
     
         18 . An integrated circuit, comprising:
 a plurality of layers of bitlines;   a plurality of layers of wordlines;   a plurality of decks of memory cells configured in an array, each of the decks being between a layer of bitlines among the plurality of layers of bitlines and a layer of wordlines among the plurality of layers of wordlines, each of the layer of bitlines connected to a row of memory cells in the array, and each of the layer of wordlines connected to a column of memory cells in the array;   bitline drivers connected to the plurality of layers of bitlines;   wordline drivers connected to the plurality of layers of wordlines, wherein each respective memory cell in the decks is connected to a bitline driver and a wordline driver, wherein the bitline driver and the wordline driver are configured to apply a voltage in a positive polarity when a voltage driven by the bitline driver is higher than a voltage driven by the wordline driver, and a negative polarity when a voltage driven by the bitline driver is lower than a voltage driven by the wordline driver; and   a controller configured to:
 make a determination to skip a drift cancellation pulse to the respective memory cell prior to applying a programming pulse to the respective memory cell, in response to a command to store predetermined data in the respective memory cell; and 
 program, based on the determination, a threshold voltage of the respective memory cell using the programming pulse according to the predetermined data without applying the drift cancellation pulse; 
   wherein in absence of the determination, the controller is configured to apply the drift cancellation pulse to the respective memory cell before programming the respective memory cell using the programming pulse.   
     
     
         19 . The integrated circuit of  claim 18 , wherein the threshold voltage of the respective memory cell is programmable to be in a first state via a first voltage driver and a second voltage driver driving a first voltage pulse on the respective memory cell in a first polarity in which a voltage driven by the first voltage driver is higher than a voltage driven by the second voltage driver; and
 wherein the drift cancellation pulse includes a second voltage pulse on the respective memory cell in a second polarity, opposite to the first polarity; and   wherein a voltage driven by the first voltage driver is lower than a voltage driven by the second voltage driver in the second polarity.   
     
     
         20 . The integrated circuit of  claim 18 , wherein the determination to skip the drift cancellation pulse is based on an attribute of the respective memory cell; and
 wherein the attribute is based at least in part on a location of the respective memory cell, an address of the respective memory cell, an electrical distance from the respective memory cell to the two voltage drivers, or a timing of a command to store data into the respective memory cell, or any combination thereof.