Plate node configurations and operations for a memory array

Abstract

Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

1 . (canceled) 
     
     
         2 . An apparatus, comprising:
 a first deck of memory cells, each memory cell of the first deck of memory cells comprising a respective first capacitor and a respective first selection component;   a second deck of memory cells positioned between the first deck of memory cells and a substrate, each memory cell of the second deck of memory cells comprising a respective second capacitor and a respective second selection component;   a first switching component configured to shunt a first plate node associated with the first deck of memory cells with a first digit line associated with the first deck of memory cells; and   a second switching component configured to shunt a second plate node associated with the second deck of memory cells with a second digit line associated with the second deck of memory cells.   
     
     
         3 . The apparatus of  claim 2 , wherein:
 the first deck of memory cells is positioned between a portion of the first plate node and the second deck of memory cells; and   the second deck of memory cells is positioned between a portion of the second plate node and the substrate.   
     
     
         4 . The apparatus of  claim 3 , wherein:
 the portion of first plate node and the portion of second plate node are coupled together.   
     
     
         5 . The apparatus of  claim 3 , wherein:
 the first plate node is associated with a first sheet of conductive material coupled with multiple rows of the first deck of memory cells or multiple columns of the first deck of memory cells; and   the second plate node is associated with a second sheet of conductive material coupled with multiple rows of the second deck of memory cells or multiple columns of the second deck of memory cells.   
     
     
         6 . The apparatus of  claim 3 , wherein:
 the first plate node is associated with a first plate line of a plurality of first plate lines associated with the first deck of memory cells; and   the second plate node is associated with a second plate line of a plurality of second plate lines associated with the second deck of memory cells.   
     
     
         7 . The apparatus of  claim 6 , wherein:
 the plurality of first plate lines extend along a same direction as the first digit line; and   the plurality of second plate lines extend along a same direction as the second digit line.   
     
     
         8 . The apparatus of  claim 2 , wherein:
 a portion of the first plate node and a portion of the second plate node are positioned between the first deck of memory cells and the second deck of memory cells.   
     
     
         9 . The apparatus of  claim 8 , wherein:
 the portion of first plate node and the portion of the second plate node are associated with a same plate line positioned between the first deck of memory cells and the second deck of memory cells.   
     
     
         10 . The apparatus of  claim 2 , wherein:
 the first digit line and the second digit line are positioned between the first deck of memory cells and the second deck of memory cells.   
     
     
         11 . The apparatus of  claim 10 , wherein:
 the first digit line and the second digit line are a same digit line positioned between the first deck of memory cells and the second deck of memory cells.   
     
     
         12 . The apparatus of  claim 10 , wherein:
 the first deck of memory cells is positioned between a portion of the first plate node and the first digit line; and   the second deck of memory cells is positioned between the first digit line and a portion of the second plate node.   
     
     
         13 . The apparatus of  claim 12 , wherein:
 the portion of first plate node and the portion of the second plate node are coupled together.   
     
     
         14 . The apparatus of  claim 2 , wherein the first switching component and the second switching component are included in the substrate. 
     
     
         15 . The apparatus of  claim 2 , wherein the first switching component and the second switching component are positioned proximal to an edge of an array that includes the first deck of memory cells and the second deck of memory cells. 
     
     
         16 . The apparatus of  claim 2 , further comprising:
 a third switching component operable to couple the first digit line with a sense component; and   a fourth switching component operable to couple the second digit line with the sense component.   
     
     
         17 . A method, comprising:
 selecting a first memory cell of first deck of memory cells for an access operation, the first deck of memory cells associated with a first level over a substrate;   coupling a capacitor of the first memory cell with a first digit line based at least in part on selecting the first memory cell for the access operation; and   shunting a second digit line associated with a second memory cell of a second deck of memory cells with a plate node based at least in part on selecting the first memory cell for the access operation, the second deck of memory cells associated with a second level over the substrate that is different than the first level.   
     
     
         18 . The method of  claim 17 , wherein shunting the second digit line with the plate node comprises:
 activating a switching component in the substrate that couples the second digit line with the plate node.   
     
     
         19 . The method of  claim 17 , wherein the plate node is coupled with the capacitor of the first memory cell. 
     
     
         20 . The method of  claim 17 , further comprising:
 shunting a third digit line associated with a third memory cell of the first deck of memory cells with the plate node based at least in part on selecting the first memory cell for the access operation.   
     
     
         21 . An apparatus, comprising:
 an array of memory cells that includes a first deck of memory cells associated with a first level over a substrate and a second deck of memory cells associated with a second level over the substrate that is different than the first level; and   a controller in electronic communication with the array of memory cells, wherein the controller is operable to:
 select a first memory cell of the first deck of memory cells for an access operation; 
 couple a capacitor of the first memory cell with a first digit line based at least in part on selecting the first memory cell for the access operation; and 
 shunt a second digit line associated with a second memory cell of the second deck of memory cells with a plate node based at least in part on selecting the first memory cell for the access operation.