Semiconductor device and method for forming the wiring structures avoiding short circuit thereof

Abstract

A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

1 . A semiconductor device comprising:
 a substrate;   a memory cell region over the substrate;   a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and   a plurality of first and second word-lines extending across the memory cell region and the peripheral region;   wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and   wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising an additional peripheral region over the substrate;
 wherein the memory cell region is arranged between the peripheral and the additional peripheral regions;   wherein the plurality of word-lines extend over the additional peripheral region; and   wherein the length of the second word-line in the additional peripheral region is longer than the length of the first word-line in the additional peripheral region.   
     
     
         3 . The semiconductor device of  claim 1 , further comprising a plurality of contacts connected to edge portions of the plurality of the first word-lines in the peripheral region, respectively;
 wherein a width of the edge portion of each first word-line is consistent with a width of a portion of the first word-line other than the edge portion; and   wherein a side of each of the edge portions of the plurality of the first word-lines is free from the second word-line.   
     
     
         4 . The semiconductor device of  claim 2 , further comprising a plurality of contacts connected to edge portions of the plurality of the second word-lines in the additional peripheral region, respectively;
 wherein a width of the edge portion of each second word-line is consistent with a width of a portion of the second word-line other than the edge portion; and   wherein a side of each of the edge portions of the plurality of the second word-lines is free from the first word-line.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the memory cell region includes a plurality of memory cells. 
     
     
         6 . The semiconductor device of  claim 2 , wherein the memory cell region includes a plurality of memory cells. 
     
     
         7 . The semiconductor device of  claim 3 , further comprising a contact connected to the edge portion of the first word-line in the peripheral region. 
     
     
         8 . The semiconductor device of  claim 4 , further comprising a contact connected to the edge portion of the second word-line in the additional peripheral region. 
     
     
         9 . A semiconductor device comprising:
 a substrate;   a memory cell region over the substrate;   a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and   a plurality of first and second bit-lines extending across the memory cell region and the peripheral region;   wherein the plurality of first bit-lines and the plurality of second bit-lines are arranged alternately with each other; and   wherein the length of the first bit-line in the peripheral region is longer than the length of the second bit-line in the peripheral region.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising an additional peripheral region over the substrate;
 wherein the memory cell region is arranged between the peripheral and the additional peripheral regions;   wherein the plurality of bit-lines extend over the additional peripheral region; and   wherein the length of the second bit-line in the additional peripheral region is longer than the length of the first bit-line in the additional peripheral region.   
     
     
         11 . The semiconductor device of  claim 9  further comprising a plurality of contacts connected to edge portions of the plurality of the first bit-lines in the peripheral region, respectively;
 wherein a width of the edge portion of each first bit-line is consistent with a width of a portion of the first bit-line other than the edge portion; and 
 wherein a side of each of the edge portions of the plurality of the first bit-lines is free from the second bit-line. 
 
     
     
         12 . The semiconductor device of  claim 10 , further comprising a plurality of contacts connected to edge portions of the plurality of the second bit-lines in the additional peripheral region, respectively;
 wherein a width of the edge portion of each second bit-line is consistent with a width of a portion of the second bit-line other than the edge portion; and   wherein a side of each of the edge portions of the plurality of the second bit-lines is free from the first bit-line.   
     
     
         13 . The semiconductor device of  claim 9 , wherein the memory cell region includes a plurality of memory cells. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the memory cell region includes a plurality of memory cells. 
     
     
         15 . The semiconductor device of  claim 11 , further comprising a contact connected to the edge portion of the first bit-line in the peripheral region. 
     
     
         16 . The semiconductor device of  claim 12 , further comprising a contact connected to the edge portion of the second bit-line in the additional peripheral region. 
     
     
         17 . A method comprising:
 forming a repetition of four line-shaped mask patterns extending across a memory cell region and a peripheral region provided over a substrate;   forming a first resist pattern arranged periodically on the line-shaped mask patterns so as to sandwich three of the line-shaped mask patterns in between;   forming a second resist pattern arranged periodically on the line-shaped mask patterns so as to sandwich one of the line-shaped mask patterns between the first resist pattern and the second resist pattern; and   transferring a staggered pattern to a member arranged under the line-shaped mask patterns, the staggered pattern being formed by the line-shaped mask patterns, the first resist pattern, and the second resist pattern using the line-shaped mask patterns, the first resist pattern, and the second resist pattern as masks.   
     
     
         18 . The method of  claim 17 , wherein the first resist pattern is cured before forming the second resist pattern. 
     
     
         19 . The method of  claim 17 ,
 wherein the line-shaped mask patterns are openings,   wherein, in the transferring process, the line-shaped mask patterns are transferred to the member arranged under the line-shaped mask patterns as trenches, and   wherein the method further comprises forming wiring by burying a conductive material in the trenches.   
     
     
         20 . The method of  claim 17 ,
 wherein the line-shaped mask patterns are line patterns, and   wherein, in the transferring process, a plurality of wirings are formed by transferring the line patterns to the member arranged under the line-shaped mask patterns.