Control circuit for adjusting timing of sense amplifier enable signal, and sense enable circuit and method for enabling sense amplifier

Abstract

A sense enable circuit for enabling a sense amplifier is provided. The sense enable circuit includes a signal generator circuit, a group of reference memory cells and a control circuit. The signal generator circuit is configured to generate a sense amplifier enable signal according to a trigger signal. The sense amplifier is enabled by the sense amplifier enable signal to sense data stored in a memory cell. Each reference memory cell is coupled to a reference wordline and a reference bitline. The reference wordline is activated in response to activation of a wordline coupled to the memory cell. The reference memory cell is configured to, in response to activation of the reference wordline, couple a first reference signal to the reference bitline. The control circuit is configured to adjust a signal level of the reference bitline, and generate the trigger signal according to the signal level of the reference bitline.

What is claimed is: 
     
         1 . A sense enable circuit for enabling a sense amplifier, the sense enable circuit comprising:
 a signal generator circuit, configured to generate a sense amplifier enable signal according to a trigger signal, wherein the sense amplifier is enabled by the sense amplifier enable signal to sense data stored in a memory cell;   a group of reference memory cells, each reference memory cell being coupled to a reference wordline and a reference bitline, the reference wordline being activated in response to activation of a wordline coupled to the memory cell, wherein the reference memory cell is configured to, in response to activation of the reference wordline, couple a first reference signal to the reference bitline; and   a control circuit, coupled to the reference bitline and the signal generator circuit, the control circuit being configured to adjust a signal level of the reference bitline, and generate the trigger signal according to the signal level of the reference bitline.   
     
     
         2 . The sense enable circuit of  claim 1 , wherein the sense amplifier enable signal is asserted when a signal level of the trigger signal reaches a predetermined level;
 the control circuit is configured to adjust a length of time taken for the signal level of the trigger signal to reach the predetermined level by adjusting the signal level of the reference bitline.   
     
     
         3 . The sense enable circuit of  claim 2 , wherein the trigger signal reaches the predetermined level following a signal on the reference bitline. 
     
     
         4 . The sense enable circuit of  claim 1 , wherein the control circuit comprises:
 a voltage generator circuit, configured to provide a supply voltage; and   a Schmitt trigger, having a supply terminal, an input terminal and an output terminal, wherein the supply terminal is coupled to the supply voltage, the input terminal is coupled to the reference bitline, and the output terminal is coupled to the signal generator circuit; the Schmitt trigger is configured to generate the trigger signal at the output terminal.   
     
     
         5 . The sense enable circuit of  claim 4 , wherein the Schmitt trigger comprises a transistor; wherein a control terminal, a first connection terminal and a second connection terminal of the transistor serve as the output terminal, the input terminal and the supply terminal, respectively. 
     
     
         6 . The sense enable circuit of  claim 4 , wherein the Schmitt trigger is configured to slow a rate of change of the signal level of the reference bitline when a voltage level of the supply voltage increases. 
     
     
         7 . The sense enable circuit of  claim 4 , wherein the control circuit further comprises:
 a capacitive coupling element, coupled to the reference bitline, the capacitive coupling element being configured to capacitively couple a signal level of the reference wordline to the reference bitline.   
     
     
         8 . The sense enable circuit of  claim 7 , wherein the control circuit further comprises:
 a delay circuit, coupled between the reference wordline and the capacitive coupling element, the delay circuit being configured to delay a signal applied to the reference wordline to generate a delayed signal, wherein the capacitive coupling element is configured to capacitively couple the delayed signal to the reference bitline.   
     
     
         9 . The sense enable circuit of  claim 1 , the control circuit further comprises:
 a switch coupled to the reference wordline, wherein the switch is configured to couple a second reference signal, which is different from the first reference signal, to the reference bitline before the reference wordline is activated, and uncouple the second reference signal from the reference bitline when the reference wordline is activated.   
     
     
         10 . The sense enable circuit of  claim 1 , wherein the signal generator circuit comprises:
 a NAND gate coupled between a second reference signal and the reference bitline, the second reference signal being different from the first reference signal, wherein a first input terminal and a second input terminal of the NAND gate are coupled to a read enable signal and the reference wordline, respectively; an output terminal of the NAND gate is coupled to the trigger signal; and   an inverter, wherein an input terminal of the inverter is coupled to the output terminal of the NAND gate to receive the trigger signal, and an output terminal of the inverter is arranged to output the sense amplifier enable signal.   
     
     
         11 . A control circuit for adjusting timing of a sense amplifier enable signal, the sense amplifier enable signal being asserted when a signal level of a trigger signal reaches a predetermined level, the control circuit comprising:
 a voltage generator circuit, configured to provide a supply voltage;   a capacitive coupling element, coupled to a reference bitline of a reference memory cell, the capacitive coupling element being configured to capacitively couple a signal level of a reference wordline of the reference memory cell to the reference bitline, wherein a sense amplifier is enabled by the sense amplifier enable signal to sense data stored in a memory cell, the reference wordline is activated in response to activation of a wordline coupled to the memory cell, and the reference bitline discharges in response to activation of the reference wordline; and   a trigger circuit, coupled to the reference bitline and the voltage generator circuit, the trigger circuit being configured to adjust a signal level of the reference bitline according to the supply voltage, and to produce the trigger signal according to the signal level of the reference bitline.   
     
     
         12 . The control circuit of  claim 11 , wherein the trigger signal reaches the predetermined level following a signal on the reference bitline. 
     
     
         13 . The control circuit of  claim 11 , wherein the trigger circuit is a Schmitt trigger having a supply terminal, an input terminal and an output terminal; the supply terminal is coupled to the supply voltage, the input terminal is coupled to the reference bitline, and the output terminal is arranged to output the trigger signal. 
     
     
         14 . The control circuit of  claim 13 , wherein the Schmitt trigger comprises a transistor; wherein a control terminal, a first connection terminal and a second connection terminal of the transistor serve as the output terminal, the input terminal and the supply terminal, respectively. 
     
     
         15 . The control circuit of  claim 11 , wherein when a voltage level of the supply voltage increases, the trigger circuit is configured to slow a rate of change of the signal level of the reference bitline. 
     
     
         16 . The control circuit of  claim 11 , further comprising:
 a delay circuit, coupled between the reference wordline and the capacitive coupling element, the delay circuit being configured to delay a signal applied to the reference wordline to generate a delayed signal, wherein the capacitive coupling element is configured to capacitively couple the delayed signal to the reference bitline.   
     
     
         17 . The control circuit of  claim 11 , further comprising:
 a switch coupled to the reference wordline, wherein the switch is configured to couple a reference signal to the reference bitline before the reference wordline is activated, and uncouple the reference signal from the reference bitline when the reference wordline is activated.   
     
     
         18 . A method for operating a sense amplifier, comprising:
 discharging a reference bitline of a reference memory cell in response to activation of a wordline coupled to a memory cell, wherein data stored in the memory cell is outputted to the sense amplifier in response to activation of the wordline;   capacitively coupling a signal level of a reference wordline of the reference memory cell to the reference bitline, wherein the reference wordline is activated in response to activation of the wordline;   adjusting a signal level of the reference bitline to increase a length of time taken for the signal level of the reference bitline to reach a predetermined level; and   generating a sense amplifier enable signal according to the signal level of the reference bitline, wherein the sense amplifier enable signal is asserted to enable the sense amplifier when the signal level of the reference bitline reach the predetermined level.   
     
     
         19 . The method of  claim 18 , wherein the step of capacitively coupling the signal level of the reference wordline to the reference bitline comprises:
 delaying a signal applied to the reference wordline to generate a delayed signal; and   coupling the delayed signal to the reference bitline, thereby capacitively coupling the signal level of the reference wordline to the reference bitline.   
     
     
         20 . The method of  claim 18 , further comprising:
 before the reference wordline is activated, coupling a reference signal to the reference bitline; and   when the reference wordline is activated, uncoupling the reference signal from the reference bitline.