Graphics engine partitioning mechanism

Abstract

An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

1 - 20 . (canceled) 
     
     
         21 . An apparatus comprising:
 one or more graphics processing units (GPUs) including a plurality of graphics processing engines, the plurality of graphics processing engines including a plurality of subsets of engines including at least a first subset of engines including one or more graphics processing engines and a second subset of engines including one or more graphics processing engines, and wherein the one or more GPUs are to support a plurality of virtual machines (VMs), including a first VM and a second VM; and   a multi-function configurable interface including a plurality of configurable circuits;   wherein each configurable circuit of the plurality of configurable circuits includes a plurality of components, the plurality of components of each configurable circuit including a respective component that is dedicated to provide access to each of the subsets of engines.   
     
     
         22 . The apparatus of  claim 21 , wherein the plurality of configurable circuits includes one or more of:
 a first configurable circuit to provide independent register access,   a second configurable circuit to provide independent reset control, and   a third configurable circuit to provide independent power management for each of the plurality of VMs.   
     
     
         23 . The apparatus of  claim 21 , further comprising an engine synchronization circuit to maintain synchronization between the plurality of graphics processing engines. 
     
     
         24 . The apparatus of  claim 21 , wherein the one or more GPUs are to partition the plurality of graphics processing engines to facilitate independent access to each subset of engines by a respective VM of the plurality of VMs. 
     
     
         25 . The apparatus of  claim 24 , wherein the partitioning of the plurality of graphics processing engines including the one or more GPUs to configure the plurality of configurable circuits such that access to the first subset of engines can be provided to the first VM without providing the first VM access to the second subset of engines and such that operation of the first subset of engines does not interfere with operation of the second subset of engines. 
     
     
         26 . The apparatus of  claim 21 , wherein the plurality of subsets of engines includes a first subset of 3D (three-dimensional) render engines, a second subset of video encoder/decoder engines, and a third subset of video enhancement and display engines. 
     
     
         27 . The apparatus of  claim 21 , wherein the first configurable circuit includes a plurality of components, the plurality of components including a respective component that is dedicated to provide access to each of the plurality of subsets of engines. 
     
     
         28 . The apparatus of  claim 21 , wherein the plurality of graphics processing engines form one power management domain and interact to determine when a system is idle and can be powered off. 
     
     
         29 . The apparatus of  claim 21 , wherein the plurality of graphics processing engines comprise one or more of:
 a subset of one or more render engines;   a subset of one or more video decoder/encoder engines; and   a subset of one or more video enhancement engines, and a subset of one or more display engines.   
     
     
         30 . A system comprising:
 one or more processors including one or more graphics processing units (GPUs), wherein the one or more GPUs include a plurality of graphics processing engines, the plurality of graphics processing engines including a plurality of subsets of engines including a first subset of engines including one or more graphics processing engines and a second subset of engines including one or more graphics processing engines, and wherein the one or more GPUs are to support a plurality of virtual machines (VMs), including a first VM and a second VM;   a memory for storage of data, including graphics processing data; and   a multi-function configurable interface including a plurality of configurable circuits;   wherein each configurable circuit of the plurality of configurable circuits includes a plurality of components, the plurality of components of each configurable circuit including a respective component that is dedicated to provide access to each of the subsets of engines.   
     
     
         31 . The system of  claim 30 , wherein the plurality of configurable circuits includes one or more of:
 a first configurable circuit to provide independent register access,   a second configurable circuit to provide independent reset control, and   a third configurable circuit to provide independent power management for each of the plurality of VMs.   
     
     
         32 . The system of  claim 30 , wherein the one or more GPUs further include an engine synchronization circuit to maintain synchronization between the plurality of graphics processing engines. 
     
     
         33 . The system of  claim 30 , wherein the one or more GPUs are to partition the plurality of graphics processing engines to facilitate independent access to each subset of engines by a respective VM of the plurality of VMs. 
     
     
         34 . The system of  claim 33 , wherein the partitioning of the plurality of graphics processing engines includes the one or more GPUs to configure the plurality of configurable circuits such that access to the first subset of engines can be provided to the first VM without providing the first VM access to the second subset of engines and such that operation of the first subset of engines does not interfere with operation of the second subset of engines. 
     
     
         35 . The system of  claim 30 , wherein the plurality of subsets of engines includes a first subset of 3D (three-dimensional) render engines, a second subset of video encoder/decoder engines, and a third subset of video enhancement and display engines. 
     
     
         36 . The system of  claim 30 , wherein the first configurable circuit includes a plurality of components, the plurality of components including a respective component that is dedicated to provide access to each of the plurality of subsets of engines. 
     
     
         37 . One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
 initializing a plurality of virtual machines (VMs) in a system, the system including one or more processors including one or more graphics processing units (GPUs), wherein the one or more GPUs include a plurality of graphics processing engines, the plurality of graphics processing engines including a plurality of subsets of engines including a first subset of engines including one or more graphics processing engines and a second subset of engines including one or more graphics processing engines; and   partitioning the plurality of graphics processing engines to facilitate independent access to each graphics processing engine within the plurality of graphics processing engines by a respective VM of the plurality of VMs;   wherein each configurable circuit of the plurality of configurable circuits includes a plurality of components, the plurality of components of each configurable circuit including a respective component that is dedicated to provide access to each of the subsets of engines.   
     
     
         38 . The non-transitory computer-readable storage mediums of  claim 37 , wherein the plurality of configurable circuits includes one or more of:
 a first configurable circuit to provide independent register access,   a second configurable circuit to provide independent reset control, and   a third configurable circuit to provide independent power management for each of the plurality of VMs.   
     
     
         39 . The non-transitory computer-readable storage mediums of  claim 37 , further having stored thereon instructions that, when executed the by one or more processors, cause the one or more processors to perform operations comprising:
 maintaining synchronization between the plurality of graphics processing engines utilizing an engine synchronization circuit.   
     
     
         40 . The non-transitory computer-readable storage mediums of  claim 37 , further having stored thereon instructions that, when executed the by one or more processors, cause the one or more processors to perform operations comprising:
 partitioning the plurality of graphics processing engines to facilitate independent access to each subset of engines by a respective VM of the plurality of VMs.