Hybrid bonding based manufacture of light emitting diodes

Abstract

Disclosed are techniques for manufacturing LEDs. In some examples, a first component is hybrid bonded to a second component through bonding together dielectric materials of the first component and the second component, and then bonding together metal contacts of the first component and the second component. The first component comprises a semiconductor layer stack that includes an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. Prior to hybrid bonding, the first component is subjected to p-side processing, which can involve, among other things, forming a plurality of mesa shapes within the n-side semiconductor layer, the active light emitting layer, and the p-side semiconductor layer. In some examples, n-side processing is performed after the hybrid bonding. The n-side processing can modify a structure or composition of the n-side semiconductor layer, the active light emitting layer, the p-side semiconductor layer, or any combination thereof.

What is claimed is: 
     
         1 . A method comprising:
 performing p-side processing of a first component, wherein:
 the first component comprises a semiconductor layer stack including an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer, the p-side processing comprises forming a plurality of mesa shapes within the n-side semiconductor layer, the active light emitting layer, and the p-side semiconductor layer, and 
 the p-side processing is performed from a direction adjacent to a surface of the p-side semiconductor layer that is opposite to the active light emitting layer; 
   performing hybrid bonding of the first component to a second component after the p-side processing has been performed, the hybrid bonding comprising:
 bonding a dielectric material of the first component to a dielectric material of the second component, and 
 bonding metal contacts of the first component to metal contacts of the second component after the dielectric material of the first component has been bonded to the dielectric material of the second component; and 
 performing n-side processing after the hybrid bonding has been performed, wherein: 
 the n-side processing is performed from a direction adjacent to a surface of the n-side semiconductor layer that is opposite to the active light emitting layer, and 
 the n-side processing modifies a structure or composition of at least one of the n-side semiconductor layer, the active light emitting layer, or the p-side semiconductor layer. 
   
     
     
         2 . The method of  claim 1 , wherein the p-side processing, the n-side processing, or both the p-side processing and the n-side processing involves implanting ions into the semiconductor layer stack. 
     
     
         3 . The method of  claim 2 , wherein ions are implanted to a depth within the p-side semiconductor layer. 
     
     
         4 . The method of  claim 2 , wherein ions are implanted to a depth within the active light emitting layer. 
     
     
         5 . The method of  claim 2 , wherein ions are implanted to a depth within the n-side semiconductor layer. 
     
     
         6 . The method of  claim 2 , wherein at least some ions are implanted during the n-side processing. 
     
     
         7 . The method of  claim 6 , wherein the p-side processing and the n-side processing both involve implanting ions into the semiconductor layer stack. 
     
     
         8 . The method of  claim 2 , further comprising:
 annealing the semiconductor layer stack after ions have been implanted during the p-side processing, the n-side processing, or both, wherein the annealing causes implanted ions to intermix with atoms within an outer region of the semiconductor layer stack.   
     
     
         9 . The method of  claim 8 , wherein the annealing increases a bandgap at edges of one or more quantum wells in the active light emitting layer. 
     
     
         10 . The method of  claim 8 , wherein at least part of the annealing of the semiconductor layer stack is performed after implanting ions during the n-side processing. 
     
     
         11 . The method of  claim 10 , wherein the annealing of the semiconductor layer stack comprises:
 a first annealing step after implanting ions during the p-side processing; and   a second annealing step after implanting ions during the n-side processing.   
     
     
         12 . The method of  claim 1 , wherein the n-side processing comprises:
 removing a substrate from the semiconductor layer stack; and   forming optics corresponding to the plurality of mesa shapes, after the substrate has been removed.   
     
     
         13 . The method of  claim 1 , wherein the n-side processing comprises:
 etching the semiconductor layer stack to singulate light emitting diodes corresponding to the plurality of mesa shapes.   
     
     
         14 . The method of  claim 13 , wherein the etching produces trenches between adjacent mesa shapes. 
     
     
         15 . The method of  claim 1 , further comprising:
 forming a cap layer and a dielectric layer over a first mesa shape of the plurality of mesa shapes, wherein the dielectric layer is formed to have a higher level of strain than the cap layer, and wherein the strain in the dielectric layer induces quantum well intermixing in the first mesa shape.   
     
     
         16 . The method of  claim 15 , wherein the cap layer is formed over a central portion of the first mesa shape, and wherein the dielectric layer is formed outside the central portion and adjacent to the cap layer. 
     
     
         17 . The method of  claim 15 , wherein the cap layer is unstrained or lightly strained, and wherein the dielectric layer is highly strained. 
     
     
         18 . The method of  claim 15 , wherein the cap layer and the dielectric layer differ in thickness. 
     
     
         19 . The method of  claim 15 , wherein the dielectric layer extends down a side of the first mesa shape, past the active light emitting layer in the first mesa shape. 
     
     
         20 . The method of  claim 15 , wherein the dielectric layer comprises a strained SiN material created through mixed-frequency plasma enhanced chemical vapor deposition (PECVD).