US2022393594A1PendingUtilityA1
Multi-level buck converter and associate control circuit thereof
Assignee: MONOLITHIC POWER SYSTEMS INCPriority: May 26, 2021Filed: May 26, 2021Published: Dec 8, 2022
Est. expiryMay 26, 2041(~14.8 yrs left)· nominal 20-yr term from priority
H02M 3/07H02M 3/158H02M 7/4837H02M 1/0003H02M 3/1586H02M 3/157H02M 1/088H02M 1/36Y02B70/10H02M 3/155
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Claims
Abstract
A control circuit for controlling multi-level buck converter. The multi-level buck converter has N pairs of switches, and N is an integer equal to or greater than 2. The control circuit has a comparing circuit comparing a voltage feedback signal with a reference signal to generate a comparing signal, a selecting circuit receiving the comparing signal to generate N set signals, and N COT controllers. The N set signals take turns to change from inactive state to active state at each rising edge of the comparing signal. Each of the N COT controllers receives output voltage signal, input voltage signal and one corresponding set signal of N set signals to generate a corresponding control signal to control the corresponding pair of switches to perform a complementary on and off switching.
Claims
exact text as granted — not AI-modifiedI/We claim:
1 . A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2, the control circuit comprising:
a comparing circuit, configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal; a selecting circuit, configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and N COT controllers, wherein for each i=1, 2, . . . , N, the i th COT controller is configured to receive a corresponding i th set signal of the N set signals, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an i th control signal to control a corresponding i th pair of switches of the N pairs of switches to perform a complementary on and off switching based on the corresponding i th set signal, the output voltage signal and the input voltage signal.
2 . The control circuit of claim 1 , wherein the comparing circuit comprises:
an error amplifier, configured to receive the reference signal with the voltage feedback signal, and further configured to compare the reference signal with the voltage feedback signal to generate an error signal, wherein the error signal is indicative of the difference of the voltage feedback signal and the reference signal; N ramp generators, configured to generate N ramp signals, wherein for each i=1, 2, . . . , N, the i th ramp generator is configured to receive the i th control signal, and further configured to generate a corresponding i th ramp signal of the N ramp signals based on the i th control signal; an adder, configured to conduct an add operation of the voltage feedback signal and the N ramp signals to generate a sum signal; and a voltage comparator, configured to compare the sum signal with the error signal to generate the comparing signal.
3 . The control circuit of claim 1 , wherein the control circuit further comprises a delay circuit; and wherein
the delay circuit is configured to receive the input voltage signal, the output voltage signal and the N set signals, and further configured to generate N delay set signals based on the input voltage signal, the output voltage signal and the N set signals; and wherein for each i=1, 2, . . . , N, the i th COT controller is configured to receive a corresponding i th delay set signal of the N delay set signals, the output voltage signal and the input voltage signal, and further configured to generate the i th control signal based on the corresponding i th delay set signal, the output voltage signal and the input voltage signal.
4 . The control circuit of claim 3 , wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein
for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay a corresponding (2i−1) th set signal of the N set signals to generate a corresponding (2i−1) th delay set signal of the N delay set signals once the output voltage signal falls in
(
1
±
k
%
)
×
1
N
of the input voltage signal,
(
1
±
k
%
)
×
2
N
of the input voltage signal, . . . , or
(
1
±
k
%
)
×
N
-
1
N
of the input voltage signal, wherein k is a proportional coefficient.
5 . The control circuit of claim 3 , wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein
for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay a corresponding (2i+1) th set signal of the N set signals to generate a corresponding (2i+1) th delay set signal of the N delay set signals once the output voltage signal falls in
(
1
±
k
%
)
×
1
N
of the input voltage signal,
(
1
±
k
%
)
×
2
N
of the input voltage signal, . . . , or
(
1
±
k
%
)
×
N
-
1
N
of the input voltage signal, wherein k is a proportional coefficient.
6 . The control circuit of claim 3 , wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein
for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay a corresponding (2i) th set signal of the N set signals to generate a corresponding (2i) th delay set signal of the N delay set signals once the output voltage signal falls in
(
1
±
k
%
)
×
1
N
of the input voltage signal,
(
1
±
k
%
)
×
2
N
of the input voltage signal, . . . , or
(
1
±
k
%
)
×
N
-
1
N
of the input voltage signal, wherein k is a proportional coefficient.
7 . The control circuit of claim 3 , wherein when N is an even number, N/2 set signals are delayed, and wherein
for each i=1, . . . , N/2, the delay circuit is configured to delay a corresponding (2i−1) th set signal of the N set signals to generate a corresponding (2i−1) th delay set signal of the N delay set signals once the output voltage signal falls in
(
1
±
k
%
)
×
1
N
of the input voltage signal, . . . , or
(
1
±
k
%
)
×
N
-
1
N
of the input voltage signal, wherein k is a proportional coefficient.
8 . The control circuit of claim 3 , wherein when N is an even number, N/2 set signals are delayed, and wherein
for each i=1, . . . , N/2, the delay circuit is configured to delay a corresponding (2i) th set signal of the N set signals to generate a corresponding (2i) th delay set signal of the N delay set signals once the output voltage signal falls in
(
1
±
k
%
)
×
1
N
of the input voltage signal, . . . , or
(
1
±
k
%
)
×
N
-
1
N
of the input voltage signal, wherein k is a proportional coefficient.
9 . The control circuit of claim 3 , wherein the delay circuit comprises:
a voltage divider, configured to receive the input voltage signal to generate N−1 dividing voltage signals, wherein for each i=1, . . . , N−1, a corresponding i th dividing voltage signal of the N−1 dividing voltage signals is equal to i/N of the input voltage signal; N−1 hysteresis comparators, configured to generate N−1 determining signals, wherein for each i=1, . . . , N−1, the i th hysteresis comparator is configured to receive the output voltage signal and the corresponding i th dividing voltage signal, and further configured to compare the output voltage signal with the corresponding i th dividing voltage signal to generate a corresponding i th determining signal of the N−1 determining signal; an OR logic gate, configured to receive the N−1 determining signals, and configured to conduct a logic OR operation of the N−1 determining signals to generate a delay enable signal; and a plurality of delay modules, wherein each of the plurality of delay modules is configured to receive the delay enable signal and one corresponding set signal of the N set signals, and further configured to generate one corresponding delay set signal based on the delay enable signal and the one corresponding set signal.
10 . The control circuit of claim 9 , wherein when N is an odd number, the quantity of the delay modules is equal to (N−1)/2, and wherein when N is an even number, the quantity of the delay modules is equal to N/2.
11 . The control circuit of claim 1 , wherein for each i=1, 2, . . . , N, the i th COT controller comprises:
an ON time generator, configured to receive the corresponding i th set signal, the input voltage signal and the output voltage signal, and further configured to generate an on time signal based on the corresponding i th set signal, the input voltage signal and the output voltage signal; and a logic circuit, configured to receive the corresponding i th set signal and the on time signal, and further configured to conduct a logic operation of the corresponding i th set signal and the on time signal to generate the i th control signal.
12 . The control circuit of claim 11 , wherein the ON time generator comprises:
a controlled current generator, having a first terminal configured to receive the input voltage signal and a second terminal, wherein the controlled current generator is configured to generate a controlled current signal at its second terminal based on the input voltage signal; a capacitor, connected between the second terminal of the controlled current generator and the logic ground; a controlled voltage generator, having a first terminal configured to receive the output voltage signal and a second terminal, wherein the controlled voltage generator is configured to generate a controlled voltage signal at its second terminal based on the output voltage signal; a charge comparator, having a first input terminal configured to receive the controlled voltage signal, a second input terminal configured to receive a voltage across the capacitor, and an output terminal, wherein the charge comparator is configured to compare the controlled voltage signal with the voltage across the capacitor to generate the on time signal at its output terminal; and a reset switch, having a first terminal coupled to the second terminal of the controlled current generator, a second terminal connected to the logic ground, and a control terminal receive the corresponding i th set signal.
13 . The control circuit of claim 1 , wherein the selecting circuit comprises:
an enable circuit, configured to receive the comparing signal, and further configured to generate N enable signals based on the comparing signal, wherein the N enable signals take turns to change from an inactive state to an active state; and N AND logic gates, for each i=1, 2, . . . , N, the i th AND logic gate is configured to receive a corresponding i th enable signal of the N enable signals and the comparing signal, and further configured to conduct a logic AND operation of the corresponding i th enable signal of the N enable signals and the comparing signal to generate the corresponding i th set signal.
14 . The control circuit of claim 1 , wherein each of the N pair of switches comprises a high side switch and a low side switch; and wherein
the control circuit further comprises a current limiting circuit configured to receive N current sense signals, and wherein for each i=1, 2, . . . , N, the i th current sense signal is indicative of a current flowing through the low side switch of the corresponding i th pair of switches; and wherein the current limiting circuit is further configured to respectively compare each of the N current sense signals with a current limit value to generate an over-current instruction signal; and wherein if any of the N current sense signals is larger than the current limit value, the over-current instruction signal is configured to turn all of the high side switches of the N pair of switches off.
15 . The control circuit of claim 14 , wherein the current limiting circuit comprises:
N current comparators, for each i=1, 2, . . . , N, the i th current comparator has a first input terminal configured to receive the current limit value, a second input terminal configured to receive the i th current sense signal, and an output terminal, and wherein the i th current comparator is configured to compare the i th current sense signal with the current limit value to generate an i th instruction signal at its output terminal; and a current limiting AND logic gate, configured to receive N instruction signals, and further configured to conduct a logic AND operation of the N instruction signals to generate the over-current instruction signal.
16 . The control circuit of claim 1 , wherein the N set signals take turns to change from an inactive state to an active state at each rising edge of the comparing signal.
17 . A multi-level buck converter, comprising:
N pairs of switches, serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2; a comparing circuit, configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal; a selecting circuit, configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and N COT controllers, wherein for each i=1, 2, . . . , N, the i th COT controller is configured to receive a corresponding i th set signal of the N set signals, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an i th control signal to control a corresponding i th pair of switches of the N pair of switches to perform a complementary on and off switching based on the corresponding i th set signal, the output voltage signal and the input voltage signal.
18 . A multi-level buck converter, comprising:
two pairs of switches, serially connected between an input terminal and a logic ground; a comparing circuit, configured to compare a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter with a reference signal to generate a comparing signal; a selecting circuit, configured to receive the comparing signal, and further configured to generate a first set signal and a second set signal based on the comparing signal; a first COT controller, configured to receive the first set signal, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate a first control signal to control the first pair of switches to perform a complementary on and off switching based on the first set signal, the output voltage signal and the input voltage signal; and a second COT controller, configured to receive the second set signal, the output voltage signal and the input voltage signal, and further configured to generate a second control signal to control the second pair of switches to perform a complementary on and off switching based on the second set signal, the output voltage signal and the input voltage signal.
19 . The multi-level buck converter of claim 18 , wherein the comparing circuit further comprises:
an error amplifier, configured to receive the reference signal and the voltage feedback signal, and further configured to compare the reference signal with the voltage feedback signal to generate an error signal, wherein the error signal is indicative of the difference of the voltage feedback signal and the reference signal; a first ramp generator, configured to receive the first control signal, and further configured to generate a first ramp signal based on the first control signal; a second ramp generator, configured to receive the second control signal, and further configured to generate a second ramp signal based on the second control signal; an adder, configured to conduct an add operation of the voltage feedback signal, the first ramp signal and the second ramp signal to generate a sum signal; and a voltage comparator, configured to compare the error signal with the sum signal to generate the comparing signal.
20 . The multi-level buck converter of claim 18 , wherein the control circuit further comprises a delay circuit, and wherein the delay circuit is configured to receive the input voltage signal, the output voltage signal, the first set signal and the second set signal, and further configured to delay one of the first set signal and the second set signal to generate a delay set signal when the output voltage signal falls in
1
2
×
(
1
±
k
%
)
of the input voltage signal, and wherein k is a proportional coefficient.Join the waitlist — get patent alerts
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