Method for fabricating semiconductor structure and structure thereof

Abstract

Embodiments provide a method for fabricating a semiconductor structure. The method includes: providing a substrate, where the substrate includes semiconductor channels arranged in an array along a first direction and a second direction, and a part of the substrate is exposed between adjacent semiconductor channels; forming a spacer positioned between adjacent semiconductor channels, where a top surface of the spacer is lower than top surfaces of the semiconductor channels; forming a bit line positioned in the substrate, where a top surface of the bit line contacts and connects bottom surfaces of the semiconductor channels; forming a protective layer, where a part of the protective layer is positioned on the top surface of the spacer between the semiconductor channels arranged along the second direction, and another part of the protective layer is positioned on the top surface of the spacer between the semiconductor channels arranged along the first direction.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor structure, comprising:
 providing a substrate, the substrate comprising semiconductor channels arranged in an array along a first direction and a second direction, and a part of the substrate being exposed between adjacent two of the semiconductor channels;   forming a spacer, the spacer being positioned between adjacent two of the semiconductor channels, and a top surface of the spacer being lower than top surfaces of the semiconductor channels;   forming a bit line positioned in the substrate, a top surface of the bit line contacting and connecting bottom surfaces of the semiconductor channels;   forming a protective layer, a part of the protective layer being positioned on the top surface of the spacer between adjacent two of the semiconductor channels arranged along the second direction, and another part of the protective layer being positioned on the top surface of the spacer between adjacent two of the semiconductor channels arranged along the first direction; and   forming a word line, the word line being positioned between the protective layer and the spacer.   
     
     
         2 . The method for fabricating a semiconductor structure according to  claim 1 , wherein the forming the spacer comprises: forming first spacers, part of the first spacers being arranged at intervals along the first direction, and the first spacers being positioned between the semiconductor channels arranged along the second direction;
 forming side wall layers, the side wall layers covering side walls of the semiconductor channels arranged at intervals along the first direction, and the side wall layers also covering side walls of the first spacers arranged at intervals along the first direction; and   forming second spacers, each of the second spacers being positioned between adjacent two of the side wall layers, and the first spacers, the side wall layers, and the second spacers constituting the spacer.   
     
     
         3 . The method for fabricating a semiconductor structure according to  claim 2 , wherein the forming the protective layer comprises: forming a first protective layer, the first protective layer being positioned on top surfaces of the first spacers; and
 forming second protective layers, the second protective layers being positioned on side walls of the first protective layers arranged at intervals along the first direction, the second protective layers further covering the side walls of the semiconductor channels arranged at intervals along the first direction, and the first protective layers and the second protective layers constituting the protective layer.   
     
     
         4 . The method for fabricating a semiconductor structure according to  claim 3 , wherein the forming the first protective layers comprises: forming first initial protective layers before the side wall layers are formed, the first initial protective layers being positioned on top surfaces of the first spacers and extending along the first direction; and
 etching the first initial protective layers to form the first protective layers arranged at intervals along the first direction.   
     
     
         5 . The method for fabricating a semiconductor structure according to  claim 4 , wherein the forming the second protective layers comprises: forming second initial protective layers after the second spacers are formed, the second initial protective layers covering the side walls of the first protective layers, top surfaces of the side wall layers, and entire top surfaces of the second spacers; and
 etching the second initial protective layers to form the second protective layers arranged at intervals along the first direction.   
     
     
         6 . The method for fabricating a semiconductor structure according to  claim 2 , wherein the forming the protective layer comprises: forming an initial protective layer after the second spacers are formed, the initial protective layer covering the entire top surface of the spacer, and the initial protective layer further covering part of the side walls of the semiconductor channels arranged at intervals along the first direction; and
 etching the initial protective layer to form the protective layer arranged at intervals along the first direction.   
     
     
         7 . The method for fabricating a semiconductor structure according to  claim 3 , wherein a material of the protective layer is different from a material of the spacer. 
     
     
         8 . The method for fabricating a semiconductor structure according to  claim 3 , wherein a thickness of the protective layer formed is controlled within 20-70 nm in a direction perpendicular to a surface of the substrate. 
     
     
         9 . The method for fabricating a semiconductor structure according to  claim 1 , wherein the forming the bit line comprises:
 forming a bit line metal layer, the bit line metal layer being positioned between adjacent two of the semiconductor channels arranged at intervals along the first direction;   converting a part of the substrate into an initial bit line by means of a first annealing process;   removing the bit line metal layer; and   converting the initial bit line into the bit line by means of a second annealing process.   
     
     
         10 . The method for fabricating a semiconductor structure according to  claim 9 , wherein a process temperature of the first annealing process is lower than a process temperature of the second annealing process. 
     
     
         11 . The method for fabricating a semiconductor structure according to  claim 9 , wherein the process temperature of the first annealing process is 400° C. to 700° C., and the process temperature of the second annealing process is 750° C. to 1,000° C. 
     
     
         12 . The method for fabricating a semiconductor structure according to  claim 1 , wherein the forming the word line comprises: etching the spacer to expose the side walls of the semiconductor channels;
 forming an initial word line, the initial word line being positioned on the top surface of the spacer; and   etching the initial word line using the protective layer as a mask until the spacer is exposed, a remaining part of the initial word line being used as the word line.   
     
     
         13 . The method for fabricating a semiconductor structure according to  claim 12 , wherein before forming the initial word line, the method further comprises: forming a gate dielectric layer, the gate dielectric layer covering the side walls of the semiconductor channels. 
     
     
         14 . The method for fabricating a semiconductor structure according to  claim 13 , wherein after forming the gate dielectric layer, the method further comprises: forming a diffusion barrier layer, the diffusion barrier layer being positioned on the top surface of the spacer. 
     
     
         15 . A semiconductor structure, formed by the method for fabricating the semiconductor structure according to  claim 1 .